Single Flux Quantum Integrated Circuit Design

Description

High efficiency, large scale, stationary computing systems – supercomputers and data centers – are becoming increasingly important due to the movement of data storage and processing onto remote cloud servers. This book is dedicated to a technology particularly appropriate for this application – superconductive electronics, in particular, rapid single flux quantum circuits. The primary purpose of this book is to introduce and systematize recent developments in superconductive electronics into a cohesive whole to support the further development of large scale computing systems. A brief background into the physics of superconductivity and the operation of common superconductive devices is provided, followed by an introduction into different superconductive logic families, including the logic gates, interconnect, and bias current distribution. Synchronization, fabrication, and electronic design automation methodologies are presented, reviewing both widely established concepts and techniques as well as recent approaches. Issues related to memory, synchronization, bias networks, and testability are described, and models, circuits, algorithms, and design methodologies are discussed and placed in context. The aim of this book is to provide insight and engineering intuition into the design of large scale digital superconductive circuits and systems. Preface Acknowledgments Contents 1 Introduction 1.1 Types of Computing Systems 1.2 Remote (Cloud) Computing 1.3 Superconductive Electronics 1.4 Outline 2 Physics and Devices of Superconductive Electronics 2.1 Introduction 2.2 Theories of Superconductivity 2.2.1 London Theory 2.2.1.1 Derivation of London Equations 2.2.2 Ginzburg-Landau Theory 2.2.3 Bardeen-Cooper-Schrieffer (BCS) Theory 2.3 Properties of Superconductive Materials 2.3.1 Meissner Effect 2.3.2 Quantization of Magnetic Flux 2.3.3 Energy Gap 2.3.4 Quasiparticles 2.3.5 London Penetration Depth 2.3.6 Critical Field and Critical Current 2.3.7 Coherence Length 2.3.8 Type-I and Type-II Superconductors 2.3.9 Low and High Temperature Superconductors 2.3.10 Kinetic Inductance 2.4 Josephson Junctions 2.4.1 Josephson Effects 2.4.2 Josephson Inductance 2.4.3 Josephson Energy 2.4.4 JJ Circuit Models 2.4.5 Dynamics of Josephson Junctions 2.5 Superconductive Devices 2.5.1 Superconductive Nanowire Single-Photon Detectors 2.5.2 Cryotron 2.5.3 Nanocryotron 2.5.4 Superconductor-Ferromagnetic Devices 2.5.4.1 Superconductor-Ferromagnetic Transistor 2.6 Conclusions 3 Superconductive Circuits 3.1 SQUID 3.1.1 Single Junction SQUID 3.1.2 Two Junction SQUID 3.2 Voltage Level Logic 3.3 RSFQ Logic 3.4 Reciprocal Quantum Logic 3.5 Adiabatic Superconductive Logic 3.5.1 Reversible Computing 3.5.2 Adiabatic Quantum Flux Parametron 3.6 Memory 3.6.1 Josephson Memory 3.6.2 Cryogenic CMOS Memory 3.6.3 Spin-Based Memory 3.7 Conclusions 4 Rapid Single Flux Quantum (RSFQ) Circuits 4.1 Transmission Lines 4.1.1 Josephson Transmission Lines 4.1.2 Passive Transmission Lines 4.2 Logic Gates and Flip Flops 4.2.1 D Flip Flop 4.2.2 Buffer 4.2.3 Splitter 4.2.4 Confluence Buffer 4.2.5 OR and AND Gates 4.2.6 Inverter 4.2.7 Muller C Element 4.2.8 SFQ-to-DC and DC-to-SFQ Converters 4.3 Bias Networks in RSFQ 4.3.1 Bias Distribution in RSFQ Circuits 4.3.2 Energy Efficient Bias Distribution in RSFQ Circuits 4.3.2.1 Resistive Bias Current Distribution with Low Bias Voltage 4.3.2.2 Inductive Bias Current Distribution 4.3.2.3 Dual-Rail SFQ 4.3.2.4 ERSFQ 4.3.2.5 eSFQ 4.4 Conclusions 5 Synchronization 5.1 Synchronous RSFQ Circuits 5.1.1 Common RSFQ Clocking Schemes 5.1.2 Hybrid Clocking Approaches 5.1.3 GALS 5.1.4 Dynamic SFQ 5.2 Asynchronous RSFQ Circuits 5.2.1 Handshaking Protocols 5.2.2 Dual-Rail Logic 5.3 AQFP Circuits 5.4 Conclusions 6 Superconductive IC Manufacturing 6.1 Superconductive IC Fabrication Process 6.1.1 Material Deposition 6.1.1.1 Metal Layers 6.1.1.2 Resistors 6.1.1.3 Inter-layer Dielectric 6.1.2 Patterning 6.1.3 Josephson Junctions 6.2 Manufacturing Features and Challenges 6.2.1 Planarization 6.2.2 High Kinetic Inductance Layer 6.2.3 Self-Shunted Junctions 6.2.4 3-D Integration 6.3 Conclusions 7 EDA for Superconductive Electronics 7.1 Cell Library Design and Characterization 7.2 RTL Design and Simulation 7.3 Circuit Simulation 7.4 Inductance Extraction 7.5 Logic Synthesis 7.5.1 Logic Representation 7.5.2 Path Balancing 7.6 Layout Synthesis 7.7 Timing Analysis 7.7.1 Timing Constraints 7.7.2 STA Techniques 7.8 Verification and Testability 7.9 Conclusions 8 Compact Model of Superconductor-Ferromagnetic Transistor 8.1 Introduction 8.2 Compact Model of the SFT Device 8.2.1 SFT Device Operation 8.2.2 Critical Current and Suppression of Superconductive Energy Gap 8.2.3 Gain and Threshold Voltage Model 8.2.4 Reactive Parameters of the Injector 8.2.5 Asymmetry Parameter 8.3 Model Verification 8.4 Conclusions 9 Inductive Coupling Noise in Multilayer Superconductive ICs 9.1 Sources of Inductive Noise Coupling 9.1.1 PTL Noise Coupling 9.1.2 Coupling of Bias Current 9.1.3 Techniques for Coupling Evaluation 9.2 Inductive Coupling for Common Circuit Structures 9.2.1 Existing Experimental Data 9.2.2 Coupling Between Parallel PTLs 9.2.3 Coupling Between Perpendicular PTLs With and Without Overlap 9.2.4 Coupling Between M0 Bias Lines and Logic Gates 9.3 Effects of Coupling on Circuits and Mitigation Guidelines 9.3.1 Effects of PTL Noise Coupling 9.3.2 Effects of Bias Current Coupling 9.4 Conclusions 10 Sense Amplifier for Spin-Based Cryogenic Memory Cell 10.1 Circuit Components 10.1.1 Memory Cell Readout 10.1.2 Synchronous DC/SFQ Converter as Memory Sense Amplifier 10.1.3 Sense Amplifier Topologies 10.1.3.1 Direct Connection 10.1.3.2 Additional Current Bias 10.1.3.3 Additional Flux Bias 10.2 Simulation Results 10.3 Conclusions 11 Dynamic Single Flux Quantum Majority Gates 11.1 Introduction 11.2 Dynamic SFQ Storage Loops 11.3 Circuit Design of Dynamic Loops 11.4 Majority Gates 11.5 Applications and Advantages 11.6 Conclusions 12 Wave Pipelining in DSFQ Circuits 12.1 Path Balancing and Wave Pipelining in RSFQ Systems 12.2 Path Delay Balancing in DSFQ Circuits 12.2.1 Delay Balancing 12.2.2 Inverter Propagation 12.2.3 Benchmark Circuits 12.2.4 DSFQ Circuits Without Path Balancing 12.3 Partial Path Balancing and Wave Pipelining 12.3.1 Necessary Conditions for Wave Pipelining 12.3.2 Full Path Balancing 12.3.3 Partial Path Balancing 12.3.3.1 Case Study 12.4 Conclusions 13 Design Guidelines for ERSFQ Bias Networks 13.1 Introduction 13.2 Example Circuit and Analysis Methodology 13.3 Trends and Guidelines of ERSFQ Bias Networks 13.3.1 Bias Inductance 13.3.2 Topology of FJTL Stage 13.3.3 Bias Margins of FJTL 13.3.4 Size of FJTL 13.3.5 Inductance of Bias Bus 13.4 Distributed FJTL Methodology 13.5 Conclusions 14 Partitioning RSFQ Circuits for Current Recycling 14.1 Introduction 14.2 Current Recycling 14.3 Partitioning of Arbitrary RSFQ Circuits During Placement 14.3.1 Unbalanced Partitioning of RSFQ Circuits with Padding 14.3.2 Partitioning During Placement 14.3.3 Coarse Placement 14.3.4 Partitioning Using Fiduccia-Mattheyses Heuristic 14.3.5 Geometric Partitioning with Simulated Annealing 14.4 Conclusions 15 GALS Clocking and Shared Interconnect for Large Scale SFQ Systems 15.1 Introduction 15.2 GALS Clocking Scheme for SFQ Circuits 15.2.1 Ambiguity of Clock and Data 15.2.2 Clock Generation and Distribution 15.2.3 Clock Activation Scheme 15.3 Shared Interconnect 15.3.1 Types of SFQ Interconnect 15.3.2 Input Discrimination 15.3.3 Bus Topology 15.4 Behavioral Characteristics 15.4.1 Behavior of H-Tree Clock Networks 15.4.2 Behavior of H-Tree and Concurrent Networks 15.4.3 Approaches for Clock Activation and Distribution 15.4.4 Multi-Chip Modules 15.4.5 Compatibility of Energy Efficient SFQ with Proposed Approaches 15.5 Conclusions 16 Design for Testability of SFQ Circuits 16.1 Introduction 16.2 Reducing DFT Overhead 16.2.1 Replacing Multiplexers 16.2.2 Blocking Gates 16.2.2.1 Clock-Controlled Blocking Gate 16.2.2.2 Current-Controlled Blocking Gates 16.3 Test Point Insertion for SFQ Circuits 16.3.1 Test Process 16.3.2 Comparison of Blocking Gates with Multiplexers 16.3.3 Advantages and Disadvantages of Test Point Insertion 16.4 Set/Scan Chains for SFQ Circuits 16.5 Conclusions 17 Conclusions Bibliography Index