AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing

Description

This work addresses the research and development of an innovative optimization kernel applied to analog integrated circuit (IC) design. Particularly, this works describes the modifications inside the AIDA Framework, an electronic design automation framework fully developed by at the Integrated Circuits Group-LX of the Instituto de Telecomunicações, Lisbon. It focusses on AIDA-CMK, by enhancing AIDA-C, which is the circuit optimizer component of AIDA, with a new multi-objective multi-constraint optimization module that constructs a base for multiple algorithm implementations. The proposed solution implements three approaches to multi-objective multi-constraint optimization, namely, an evolutionary approach with NSGAII, a swarm intelligence approach with MOPSO and stochastic hill climbing approach with MOSA. Moreover, the implemented structure allows the easy hybridization between kernels transforming the previous simple NSGAII optimization module into a more evolved and versatile module supporting multiple single and multi-kernel algorithms. The three multi-objective optimization approaches were validated with CEC2009 benchmarks to constrained multi-objective optimization and tested with real analog IC design problems. The achieved results were compared in terms of performance, using statistical results obtained from multiple independent runs. Finally, some hybrid approaches were also experimented, giving a foretaste to a wide range of opportunities to explore in future work.;Introduction -- Previous works on automated analog IC sizing -- AIDA-CMK: AIDA-C with MOO framework -- Multi-objective framework implementation -- Kernel validation using CEC2009 benchmarks -- Results for analog IC design -- Conclusion and Future work. Introduction -- Previous works on automated analog IC sizing -- AIDA-CMK: AIDA-C with MOO framework -- Multi-objective framework implementation -- Kernel validation using CEC2009 benchmarks -- Results for analog IC design -- Conclusion and Future work.