Introduction to Logic Circuits & Logic Design with Verilog
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1 Introduction: Analog Versus Digital 1.1 Differences Between Analog and Digital Systems 1.2 Advantages of Digital Systems over Analog Systems 2 Number Systems 2.1 Positional Number Systems 2.1.1 Generic Structure 2.1.2 Decimal Number System (Base 10) 2.1.3 Binary Number System (Base 2) 2.1.4 Octal Number System (Base 8) 2.1.5 Hexadecimal Number System (Base 16) 2.2 Base Conversion 2.2.1 Converting to Decimal 2.2.2 Converting from Decimal 2.2.3 Converting Between 2 n Bases 2.3 Binary Arithmetic 2.3.1 Addition (Carries) 2.3.2 Subtraction (Borrows) 2.4 Unsigned and Signed Numbers 2.4.1 Unsigned Numbers 2.4.2 Signed Numbers 3 Digital Circuitry and Interfacing 3.1 Basic Gates 3.1.1 Describing the Operation of a Logic Circuit 3.1.2 The Buffer 3.1.3 The Inverter 3.1.4 The AND Gate 3.1.5 The NAND Gate 3.1.6 The OR Gate 3.1.7 The NOR Gate 3.1.8 The XOR Gate 3.1.9 The XNOR Gate 3.2 Digital Circuit Operation 3.2.1 Logic Levels 3.2.2 Output DC Specifications 3.2.3 Input DC Specifications 3.2.4 Noise Margins 3.2.5 Power Supplies 3.2.6 Switching Characteristics 3.2.7 Data Sheets 3.3 Logic Families 3.3.1 Complementary Metal-Oxide Semiconductors (CMOS) 3.3.2 Transistor-Transistor Logic (TTL) 3.3.3 The 7400 Series Logic Families 3.4 Driving Loads 3.4.1 Driving Other Gates 3.4.2 Driving Resistive Loads 3.4.3 Driving LEDs 4 Combinational Logic Design 4.1 Boolean Algebra 4.1.1 Operations 4.1.2 Axioms 4.1.3 Theorems 4.1.4 Functionally Complete Operation Sets 4.2 Combinational Logic Analysis 4.2.1 Finding the Logic Expression from a Logic Diagram 4.2.2 Finding the Truth Table from a Logic Diagram 4.2.3 Timing Analysis of a Combinational Logic Circuit 4.3 Combinational Logic Synthesis 4.3.1 Canonical Sum of Products 4.3.2 The Minterm List (Σ) 4.3.3 Canonical Product of Sums (POS) 4.3.4 The Maxterm List (Π) 4.3.5 Minterm and Maxterm List Equivalence 4.4 Logic Minimization 4.4.1 Algebraic Minimization 4.4.2 Minimization Using Karnaugh Maps 4.4.3 Don’t Cares 4.4.4 Using XOR Gates 4.5 Timing Hazards and Glitches 5 Verilog (Part 1) 5.1 History of Hardware Description Languages 5.2 HDL Abstraction 5.3 The Modern Digital Design Flow 5.4 Verilog Constructs 5.4.1 Data Types 5.4.2 The Module 5.4.3 Verilog Operators 5.5 Modeling Concurrent Functionality in Verilog 5.5.1 Continuous Assignment 5.5.2 Continuous Assignment with Logical Operators 5.5.3 Continuous Assignment with Conditional Operators 5.5.4 Continuous Assignment with Delay 5.6 Structural Design and Hierarchy 5.6.1 Lower-Level Module Instantiation 5.6.2 Gate-Level Primitives 5.6.3 User-Defined Primitives 5.6.4 Adding Delay to Primitives 5.7 Overview of Simulation Test Benches 6 MSI Logic 6.1 Decoders 6.1.1 Example: One-Hot Decoder 6.1.2 Example: 7-Segment Display Decoder 6.2 Encoders 6.2.1 Example: One-Hot Binary Encoder 6.3 Multiplexers 6.4 Demultiplexers 7 Sequential Logic Design 7.1 Sequential Logic Storage Devices 7.1.1 The Cross-Coupled Inverter Pair 7.1.2 Metastability 7.1.3 The SR Latch 7.1.4 The S’R’ Latch 7.1.5 SR Latch with Enable 7.1.6 The D-Latch 7.1.7 The D-Flip-Flop 7.2 Sequential Logic Timing Considerations 7.3 Common Circuits Based on Sequential Storage Devices 7.3.1 Toggle Flop Clock Divider 7.3.2 Ripple Counter 7.3.3 Switch Debouncing 7.3.4 Shift Registers 7.4 Finite-State Machines 7.4.1 Describing the Functionality of a FSM 7.4.2 Logic Synthesis for a FSM 7.4.3 FSM Design Process Overview 7.4.4 FSM Design Examples 7.5 Counters 7.5.1 2-Bit Binary Up Counter 7.5.2 2-Bit Binary Up/Down Counter 7.5.3 2-Bit Gray Code Up Counter 7.5.4 2-Bit Gray Code Up/Down Counter 7.5.5 3-Bit One-Hot Up Counter 7.5.6 3-Bit One-Hot Up/Down Counter 7.6 Finite-State Machine’s Reset Condition 7.7 Sequential Logic Analysis 7.7.1 Finding the State Equations and Output Logic Expressions of a FSM 7.7.2 Finding the State Transition Table of a FSM 7.7.3 Finding the State Diagram of a FSM 7.7.4 Determining the Maximum Clock Frequency of a FSM 8 Verilog (Part 2) 8.1 Procedural Assignment 8.1.1 Procedural Blocks 8.1.2 Procedural Statements 8.1.3 Statement Groups 8.1.4 Local Variables 8.2 Conditional Programming Constructs 8.2.1 if-else Statements 8.2.2 case Statements 8.2.3 casez and casex Statements 8.2.4 forever Loops 8.2.5 while Loops 8.2.6 repeat Loops 8.2.7 for loops 8.2.8 disable 8.3 System Tasks 8.3.1 Text Output 8.3.2 File Input/Output 8.3.3 Simulation Control and Monitoring 8.4 Test Benches 8.4.1 Common Stimulus Generation Techniques 8.4.2 Printing Results to the Simulator Transcript 8.4.3 Automatic Result Checking 8.4.4 Using Loops to Generate Stimulus 8.4.5 Using External Files in Test Benches 9 Behavioral Modeling of Sequential Logic 9.1 Modeling Sequential Storage Devices in Verilog 9.1.1 D-Latch 9.1.2 D-Flip-Flop 9.1.3 D-Flip-Flop with Asynchronous Reset 9.1.4 D-Flip-Flop with Asynchronous Reset and Preset 9.1.5 D-Flip-Flop with Synchronous Enable 9.2 Modeling Finite-State Machines in Verilog 9.2.1 Modeling the States 9.2.2 The State Memory Block 9.2.3 The Next State Logic Block 9.2.4 The Output Logic Block 9.2.5 Changing the State Encoding Approach 9.3 FSM Design Examples in Verilog 9.3.1 Serial Bit Sequence Detector in Verilog 9.3.2 Vending Machine Controller in Verilog 9.3.3 2-Bit, Binary Up/Down Counter in Verilog 9.4 Modeling Counters in Verilog 9.4.1 Counters in Verilog Using a Single-Procedural Block 9.4.2 Counters with Range Checking 9.4.3 Counters with Enables in Verilog 9.4.4 Counters with Loads 9.5 RTL Modeling 9.5.1 Modeling Registers in Verilog 9.5.2 Registers as Agents on a Data Bus 9.5.3 Shift Registers in Verilog 10 Memory 10.1 Memory Architecture and Terminology 10.1.1 Memory Map Model 10.1.2 Volatile Versus Non-volatile Memory 10.1.3 Read-Only Versus Read/Write Memory 10.1.4 Random Access Versus Sequential Access 10.2 Non-volatile Memory Technology 10.2.1 ROM Architecture 10.2.2 Mask Read-Only Memory (MROM) 10.2.3 Programmable Read-Only Memory (PROM) 10.2.4 Erasable Programmable Read-Only Memory (EPROM) 10.2.5 Electrically Erasable Programmable Read-Only Memory (EEPROM) 10.2.6 FLASH Memory 10.3 Volatile Memory Technology 10.3.1 Static Random-Access Memory (SRAM) 10.3.2 Dynamic Random-Access Memory (DRAM) 10.4 Modeling Memory with Verilog 10.4.1 Read-Only Memory in Verilog 10.4.2 Read/Write Memory in Verilog 11 Programmable Logic 11.1 Programmable Arrays 11.1.1 Programmable Logic Array (PLA) 11.1.2 Programmable Array Logic (PAL) 11.1.3 Generic Array Logic (GAL) 11.1.4 Hard Array Logic (HAL) 11.1.5 Complex Programmable Logic Devices (CPLD) 11.2 Field-Programmable Gate Arrays (FPGAs) 11.2.1 Configurable Logic Block (or Logic Element) 11.2.2 Look-Up Tables (LUTs) 11.2.3 Programmable Interconnect Points (PIPs) 11.2.4 Input/Output Block (IOB) 11.2.5 Configuration Memory 12 Arithmetic Circuits 12.1 Addition 12.1.1 Half Adders 12.1.2 Full Adders 12.1.3 Ripple Carry Adder (RCA) 12.1.4 Carry Look Ahead Adder (CLA) 12.1.5 Adders in Verilog 12.2 Subtraction 12.3 Multiplication 12.3.1 Unsigned Multiplication 12.3.2 A Simple Circuit to Multiply by Powers of Two 12.3.3 Signed Multiplication 12.4 Division 12.4.1 Unsigned Division 12.4.2 A Simple Circuit to Divide by Powers of Two 12.4.3 Signed Division 13 Computer System Design 13.1 Computer Hardware 13.1.1 Program Memory 13.1.2 Data Memory 13.1.3 Input/Output Ports 13.1.4 Central Processing Unit 13.1.5 A Memory-Mapped System 13.2 Computer Software 13.2.1 Opcodes and Operands 13.2.2 Addressing Modes 13.2.3 Classes of Instructions 13.3 Computer Implementation: An 8-Bit Computer Example 13.3.1 Top-Level Block Diagram 13.3.2 Instruction Set Design 13.3.3 Memory System Implementation 13.3.4 CPU Implementation 13.4 Architecture Considerations 13.4.1 Von Neumann Architecture 13.4.2 Harvard Architecture Appendix A: List of Worked Examples Appendix B: Concept Check Solutions Index
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