Analog IC Reliability in Nanometer CMOS

Description

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs. Front Matter....Pages i-xvi Introduction....Pages 1-14 CMOS Reliability Overview....Pages 15-35 Transistor Aging Compact Modeling....Pages 37-77 Background on IC Reliability Simulation....Pages 79-91 Analog IC Reliability Simulation....Pages 93-149 Integrated Circuit Reliability....Pages 151-180 Conclusions....Pages 181-183 Back Matter....Pages 185-198