IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture

Description

IEEE Std 1149.7-2022 Front Cover Title page Notice and Disclaimer of Liability Concerning the Use of IEEE Standards Documents Translations Official statements Comments on standards Laws and regulations Data privacy Copyrights Photocopies Updating of IEEE Standards documents Errata Patents IMPORTANT NOTICE Participants Introduction History of the development of this standard Changes introduced by this revision Contents Figures Tables 1. Overview 1.1 Scope 1.2 Purpose 1.3 Word usage 1.4 Contrasting IEEE Std 1149.1 and this standard 1.5 Challenges 1.6 Important considerations 1.7 Nomenclature 1.7.1 References to technology and standards 1.7.2 Describing Test Access Port behaviors 1.7.3 Describing TAPs and TAP controllers 1.7.4 Describing scan exchanges 1.7.5 Describing TAP signals 1.8 Ensuring transparency to IEEE 1149.1 intellectual property 1.8.1 IEEE 1149.1 constraints 1.8.2 IEEE 1149.1 constraints/requirements balancing 1.8.3 IEEE 1149.1 upgrade path 1.9 Maximizing compatibility with 1149.1 IP 1.9.1 IEEE 1149.1 infrastructure 1.9.1.1 IEEE 1149.1 instructions 1.9.1.2 IEEE 1149.1 Scan Paths 1.9.1.3 IEEE 1149.1 boundary-scan capability 1.9.2 Test Clock treatment 1.9.2.1 Test Clock source 1.9.2.2 Test Clock shared or dedicated use 1.9.2.3 Unorthodox use of Test Clock 1.10 Scalability 1.10.1 Types of operation/capability classes 1.10.2 Signaling 1.11 Flexibility 1.11.1 Supporting various scan topologies 1.11.2 Operation with more than one scan topology/other technologies 1.12 Document content 1.12.1 Descriptive material 1.12.2 Specification material 1.13 Document organization 1.13.1 Partitioning 1.13.1.1 Foundation 1.13.1.2 TAP.7 Classes 1.13.1.3 Test description languages 1.13.1.4 Annexes 1.13.2 Pictorial view 1.14 Using the standard 1.14.1 User background knowledge 1.14.2 Types of users 1.14.2.1 Chip designer 1.14.2.2 Programmer 1.14.3 Use summary 1.15 Conventions 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions 3.2 Acronyms and abbreviations 4. TAP.7 concepts and architecture 4.1 Introduction 4.2 Concepts supporting system architecture 4.2.1 Maximizing compatibility with IEEE Std 1149.1 4.2.1.1 Hardware components 4.2.1.2 Software components 4.2.2 TAPC hierarchy 4.2.2.1 Overview 4.2.2.2 Hierarchy levels 4.2.3 Parking the TAPC state 4.2.3.1 Overview 4.2.3.2 Parking-state relationships 4.2.3.3 Parking-state terminology 4.2.3.3.1 ADTAPC selection states 4.2.3.3.2 CLTAPC selection states 4.2.3.3.3 EMTAPC selection states 4.2.3.3.4 Selection state summary 4.2.4 Choice of parking states 4.2.5 Parking methods 4.2.6 Operation of the TAP.7 Controller 4.2.6.1 TAP.7 Controller management 4.2.6.2 System and Control Paths 4.2.6.3 Power management 4.2.7 Scan topologies 4.2.7.1 Series and Star Scan Topologies 4.2.7.2 Scan Topology Training 4.2.7.3 Sharing of signaling with other technologies 4.2.7.4 Direct addressability for Star Scan Topologies 4.2.7.5 Series-Equivalent Scans for Star Scan Topologies 4.2.7.6 Output-drive characteristics 4.2.7.7 Scan formats 4.2.7.8 Interoperability 4.3 Concepts supporting pin efficiency 4.3.1 Signaling methods 4.3.2 Protocols 4.3.2.1 Protocol types 4.3.2.2 Standard Protocol 4.3.2.3 Advanced Protocol 4.3.2.3.1 Interleaving of scan and non-scan information 4.3.2.3.2 Serialization of scan information 4.3.2.4 Control Protocol 4.3.3 Advanced and Control Protocol characteristics 4.3.3.1 Packets, bit-frames, and bits 4.3.3.2 Data and control information 4.3.4 Performance 4.3.4.1 TAP operation 4.3.4.1.1 Signal timing 4.3.4.1.2 Registering of signals 4.3.4.2 Scan transfer efficiency 4.4 Concepts supporting capability 4.4.1 Concepts already described 4.4.2 Resets 4.4.3 Private commands and registers 4.5 IEEE 1149.7 architecture 4.5.1 Components 4.5.2 Reset types 4.5.3 Start-up options 4.6 Operating models 4.6.1 Model types 4.6.2 Standard models 4.6.3 Advanced models 5. T0–T3 TAP.7 operational overview 5.1 Introduction 5.2 T0 TAP.7 5.2.1 Overview 5.2.2 Operating modes and capabilities 5.2.3 Operation 5.2.3.1 Multi-TAPC architecture 5.2.3.2 Selection and deselection of EMTAPCs 5.2.4 T0 TAP.7 high-level block diagram 5.3 T1 TAP.7 5.3.1 Overview 5.3.2 Operating modes and capabilities 5.3.3 Operation 5.3.3.1 Adding TAP.7 functionality to the BYPASS and IDCODE instructions 5.3.3.2 Zero-bit DR scans 5.3.3.3 Utilizing ZBSs for TAP.7 Controller functionality 5.3.3.3.1 Locking the ZBS count 5.3.3.3.2 Control levels 5.3.3.3.3 Exiting a control level 5.3.3.3.4 Zeroing the ZBS count 5.3.3.4 EPU Operating States 5.3.3.5 Commands 5.3.3.6 Registers 5.3.3.7 Using the System and Control Paths 5.3.3.7.1 System Path 5.3.3.7.2 Control Path 5.3.3.7.3 TDO Drive Policy 5.3.3.8 EPU groups 5.3.4 T1 TAP.7 high-level block diagram 5.4 T2 TAP.7 5.4.1 Overview 5.4.2 Operating modes and capabilities 5.4.3 Operation 5.4.3.1 Overview 5.4.3.2 Using the System and Control Paths 5.4.3.3 TDO Drive Policy 5.4.3.4 STL groups 5.4.3.4.1 STL group types 5.4.3.4.2 STL Group Membership changes 5.4.4 T2 TAP.7 high-level block diagram 5.5 T3 TAP.7 5.5.1 Overview 5.5.2 Operating modes and capabilities 5.5.3 Operation 5.5.3.1 Within series and star scan topologies 5.5.3.2 T3 TAP.7 Controller addressability in a Star-4 Scan Topology 5.5.3.3 Pause-IR and Pause-DR STL groups 5.5.3.4 Series/star scan equivalency 5.5.3.4.1 Defining scan equivalency 5.5.3.4.2 Creating a Series-Equivalent Scan within a Star Scan Topology 5.5.3.5 Scan Selection Directives 5.5.3.5.1 Enabling the use of SSDs 5.5.3.5.2 Types of SSDs 5.5.3.5.3 SSD execution 5.5.3.5.4 SSD State Machine 5.5.3.6 Series-Equivalent Scan creation 5.5.3.6.1 Exclusivity of SSD and TAP.7 Controller commands 5.5.3.7 Using the System and Control Paths 5.5.3.8 TDO Drive Policy 5.5.4 T3 TAP.7 high-level block diagram 6. T4–T5 TAP.7 operational overview 6.1 Introduction 6.2 T4 TAP.7 6.2.1 Operating modes and capabilities 6.2.2 Operation 6.2.2.1 Signal behaviors 6.2.2.2 Rising and falling TMSC input sampling 6.2.2.3 Controller addressability in a Star-2 Scan Topology 6.2.2.4 RSU and APU functions 6.2.2.4.1 Bypass (BPA) 6.2.2.4.2 Check Process Active (CPA) 6.2.2.4.3 Scan Packet Active (SPA) 6.2.3 T4 TAP.7 high-level block diagram 6.3 T5 TAP.7 6.3.1 Overview 6.3.2 Operating modes and capabilities 6.3.2.1 Transport source/destinations 6.3.2.1.1 Single-client operation 6.3.2.1.2 Multi-client operation 6.3.2.1.3 Client-to-client operation 6.3.2.2 Transfer characteristics 6.3.3 Operation 6.3.3.1 Transport Control Function 6.3.3.2 TPA 6.3.4 T5 TAP.7 high-level block diagram 6.4 TAP.7 feature summary 7. System concepts 7.1 Introduction 7.2 Key system attributes 7.3 DTS/TS connectivity with a mix of technologies 7.3.1 Technology mixes 7.3.2 Technology branches 7.4 TAP.7 deployment scenarios 7.4.1 TAP.1 Series Branches 7.4.2 TAP.7 Series, Star-4, and Star-2 Branches 7.5 Chip TAPC hierarchy 7.6 Combined view of TAP connectivity and TAPC hierarchy 7.7 Chips, components, and boards 8. TAPC hierarchy 8.1 Introduction 8.2 Selection/deselection with the TAPC hierarchy 8.2.1 Selection choices 8.2.2 Selection/deselection/class relationships 8.2.3 TAPC parent/child relationships 8.3 TAPC selection/deselection characteristics 8.3.1 TAPC and scan path behavior 8.3.2 Selection/deselection mechanisms 8.3.3 Parking states and resynchronization 8.4 ADTAPC selection/deselection 8.4.1 Parking use cases 8.4.2 DTS/ADTAPC relationship 8.4.3 ADTAPC operation 8.5 CLTAPC selection/deselection 8.5.1 Parking use cases 8.5.2 ADTAPC/CLTAPC relationship 8.5.3 CLTAPC operation 8.6 EMTAPC selection/deselection 8.6.1 Parking use cases 8.6.2 CLTAPC/EMTAPC relationship 8.6.3 EMTAPC operation 8.7 Using a common selection/deselection protocol across technologies 8.8 RSU deployment 8.8.1 Use with new or existing IP 8.8.2 Using TAP pins for multiple functions 8.9 Using the TAPC hierarchy 8.9.1 Selection considerations 8.9.2 Start-up considerations 8.10 Test/debug applications and the TAPC hierarchy 8.10.1 Debug use of the TAPC hierarchy 8.10.2 Test use of the TAPC hierarchy 9. Registers, commands, and scan paths 9.1 Introduction 9.2 Command basics 9.3 Register portfolio 9.3.1 Description 9.3.1.1 Global and Local Registers 9.3.1.2 Register loads 9.3.1.3 Register reset values 9.3.2 Specifications 9.4 Command portfolio 9.4.1 Description 9.4.1.1 Command types 9.4.1.2 Store commands 9.4.1.3 Select commands 9.4.1.4 Scan commands 9.4.1.5 Enumerate commands 9.4.1.6 Private commands 9.4.1.7 Effects a TAP.7 Controller reset 9.4.2 Specifications 9.5 Representation of commands in examples 9.6 Global and Local Register programming with commands 9.7 1Scan paths 9.7.1 Conceptual and physical views 9.7.1.1 Description 9.7.1.1.1 Path characteristics 9.7.1.1.2 Conceptual path selection 9.7.1.1.3 Physical path selection 9.7.1.2 Specifications 9.7.2 EPU Scan Paths and their selection 9.7.2.1 Description 9.7.2.2 Specifications 9.7.3 EPU Scan Path characteristics 9.7.3.1 Description 9.7.3.1.1 Scan-path continuity 9.7.3.1.2 EPU Bypass-Path characteristics 9.7.3.1.3 EPU Bit-Path characteristics 9.7.3.1.4 EPU String-Path characteristics 9.7.3.1.5 Enumerate-Path characteristics 9.7.3.1.6 Auxiliary Path 9.7.3.2 Specifications 9.8 Two-part commands 9.9 Three-part commands 9.9.1 SCNB Command characteristics 9.9.2 SCNS Command characteristics 9.9.3 CIDA Command characteristics 9.10 RDBACKx and CNFGx Registers 9.10.1 RDBACKx Registers 9.10.1.1 Description 9.10.1.2 Specifications 9.10.2 CNFGx Registers 9.10.2.1 Description 9.10.2.1.1 Overview 9.10.2.1.2 CNFG0 mandatory configuration information 9.10.2.1.3 CNFG0 optional configuration information 9.10.2.1.4 CNFG1 optional configuration information 9.10.2.1.5 CNFG2 and CNFG3 Registers 9.10.2.1.6 Determining the TAP type and class using configuration information 9.10.2.2 Specifications 9.11 An approach to implementing command processing and scan paths 10. RSU ancillary services 10.1 Introduction 10.2 Resets 10.2.1 Description 10.2.1.1 Overview 10.2.1.2 Reset considerations 10.2.1.3 Reset effects 10.2.1.3.1 Type-5 Reset 10.2.1.3.2 Type-4 Reset 10.2.1.3.3 Type-3 Reset 10.2.1.3.4 Type-2 Reset 10.2.1.3.5 Type-1 Reset 10.2.1.3.6 Type-0 Reset 10.2.1.3.7 Type-0 versus a Type-2 Reset 10.2.1.4 144BTAP.7 Controller operation is ensured after power-up 10.2.1.5 Other effects of a TAP.7 Controller reset 10.2.1.6 An approach to implementing TAP.7 Controller resets 10.2.2 Specifications 10.3 Start-up options 10.3.1 Description 10.3.1.1 Overview 10.3.1.2 1149.1-compliant behavior start-up option 10.3.1.3 1149.1-Compatible Start-up option 10.3.1.4 IEEE 1149.1-Protocol Compatible 10.3.1.5 Offline-at-Start-up option 10.3.1.6 Start-up behavior 10.3.2 Specifications 10.4 Escape Detection 10.4.1 Description 10.4.1.1 Overview 10.4.1.2 Detection 10.4.1.2.1 Custom Escape 10.4.1.2.2 Selection and Deselection Escapes 10.4.1.3 Reset Escape 10.4.1.4 Timing considerations 10.4.1.5 An approach to implementing Escape Detection 10.4.2 Specifications 10.5 Selection Alert 10.5.1 Description 10.5.1.1 Overview 10.5.1.2 Selection Alert Bit Sequence 10.5.1.3 Selection Alert detection 10.5.1.4 An approach to implementing Selection Alerts 10.5.2 Specifications 10.6 Deselection Alert 10.6.1 Description 10.6.2 Specifications 10.7 Programming considerations 10.7.1 Resets 10.7.2 Escapes 10.7.3 Selection Alerts 10.7.4 Test and debug 10.7.5 Concurrent use of a Selection Escape and Selection Alert 10.8 ADTAPC State Machine 10.8.1 Need 10.8.2 An approach to implementing the ADTAPC 11. RSU Online/Offline capability 11.1 Introduction 11.2 Managing Online/Offline operation 11.3 Online/Offline operating principles 11.3.1 Conceptual view of Online/Offline operation 11.3.2 Events affecting Online/Offline operation 11.3.3 Summary of responses to selection/deselection events 11.3.4 Interoperability with other technologies 11.4 Initiating Offline operation 11.4.1 Description 11.4.1.1 Events initiating Offline operation 11.4.1.2 Escapes 11.4.1.3 Alerts 11.4.1.4 Use of an unsupported feature 11.4.1.5 Offline-at-Start-up 11.4.2 Specifications 11.5 Initiating Online operation 11.5.1 Description 11.5.2 Specifications 11.6 Context-sensitive response to Selection and Deselection Escapes 11.6.1 Description 11.6.1.1 Escape qualification criteria during Online operation 11.6.1.2 Escape qualification criteria during Offline-at-Start-up operation 11.6.1.3 Selection Alert during Offline-at-Start-up operation 11.6.2 Specifications 11.7 Selection Sequence 11.7.1 Initiation 11.7.2 Format 11.7.3 Technology-independent portion 11.7.4 Technology-dependent portion 11.7.5 Forms of Selection Sequence 11.7.6 Online Activation Code 11.7.6.1 Description 11.7.6.2 Specifications Figure 11-9 — Selection Escape/subsequent data timing relationship Figure 11-10 — Selection Alert/subsequent data timing relationship 11.7.7 TAP.7 Extension Code 11.7.7.1 Description 11.7.7.2 Specifications 11.7.8 Global Register load 11.7.8.1 Description 11.7.8.2 Specifications 11.7.9 Check Packet 11.7.9.1 Description 11.7.9.1.1 Format 11.7.9.1.2 Function 11.7.9.1.3 Directives 11.7.9.2 Specifications 11.8 Parking-state considerations 11.8.1 Description 11.8.2 Specifications 11.9 Control State Machine 11.9.1 Mandatory and optional behaviors 11.9.1.1 Description 11.9.1.2 Specifications 11.9.2 Standard state (STD) 11.9.2.1 Description 11.9.2.2 Specifications 11.9.3 Advanced state (ADV) 11.9.3.1 Description 11.9.3.2 Specifications 11.9.4 Offline waiting state (OLW) 11.9.4.1 Description 11.9.4.2 Specifications 11.9.5 Test state (TEST) 11.9.5.1 Description 11.9.5.1.1 Selection test 11.9.5.1.2 Factors requiring a Global Register load for placement Online 11.9.5.1.3 ADTAPC resynchronization 11.9.5.1.4 Priority of conditions causing state changes 11.9.5.1.5 Test state function 11.9.5.1.6 Selection Sequences requiring a state load 11.9.5.2 Specifications 11.9.6 Check Packet state (CHK) 11.9.6.1 Description 11.9.6.1.1 CHK substates 11.9.6.1.2 CP examples 11.9.6.2 Specifications 11.9.7 Offline-at-Start-up state (OLS) 11.9.7.1 Description 11.9.7.1.1 Placement Online 11.9.7.1.2 CLTAPC state initialization 11.9.7.1.3 Selection Escape qualification in the OLS state 11.9.7.1.4 Example of exiting the OLS state 11.9.7.2 Specifications 11.9.7.3 An approach to implementing the CSM 11.10 Programming considerations 11.10.1 Escapes 11.10.1.1 Selection Escape 11.10.1.2 Deselection Escape 11.10.1.3 Reset Escape 11.10.2 Alerts 11.10.2.1 Deselection Alert 11.10.2.2 Selection Alert 11.10.2.3 Offline-at-Start-up 11.10.3 Selection Sequences 11.10.3.1 DTS/TAP.7 Controller synchronization 11.10.3.2 Short Form 11.10.3.3 Long Form 11.10.4 Hang caused by a programming error 12. TAP signals 12.1 Introduction 12.2 TAP.7 Class/signal relationships 12.2.1 Description 12.2.2 Specifications 12.3 Signal function and bias 12.3.1 Description 12.3.2 Specifications 12.4 Test Reset (nTRST and nTRST_PD) signals 12.4.1 Description 12.4.2 Specifications 12.5 TAP.7 signal functions with corresponding IEEE 1149.1 names 12.5.1 Description 12.5.2 Specifications 12.6 Test Clock (TCK) 12.6.1 Description 12.6.2 Specifications 12.7 Test Mode Select (TMS/TMSC) 12.7.1 Description 12.7.1.1 Online start-up 12.7.1.2 Offline start-up 12.7.1.3 Combined view of Online and Offline-at-Start-up TMS(C) signal behaviors 12.7.2 Specifications 12.8 Test Data Input (TDI/TDIC) 12.8.1 Description 12.8.2 Specifications 12.9 Test Data Output (TDO/TDOC) 12.9.1 Description 12.9.2 Specifications 12.10 Offline-at-Start-up behavior 12.10.1 Description 12.10.2 Specifications 12.11 TAP connections 12.11.1 Description 12.11.2 Specifications 12.12 Applicability of this standard 12.12.1 Description 12.12.2 Specifications 12.13 Recommendations for interoperability 12.13.1 Overview 12.13.2 Power-up behavior 12.13.3 IEEE 1149.7-Non-disruptive behavior 12.13.3.1 Description 12.13.3.2 Specifications 12.13.4 IEEE 1149.7-Other Behavior 12.13.4.1 Description 12.13.4.2 Specifications 13. TDO(C) Signal Drive Policy 13.1 Introduction 13.2 TDO(C) Signal Drive Types 13.2.1 TDO(C) Signal Drive Types 13.2.1.1 Single Drive 13.2.1.2 Joint Drive 13.2.1.3 Voting Drive 13.2.1.4 Inhibited Drive 13.2.2 Wire-ANDed TDOC data created with a combination of drives 13.3 Factors affecting the TDO(C) Drive Policy 13.4 TDO(C) Drive Policy template 13.4.1 General characteristics 13.4.2 TDOC drive enables 13.4.3 TDO(C) Drive Policy components 13.4.4 TAP.7 Class/TDO(C) Drive Policy component applicability 13.4.5 Dormant TDO(C) Drive Policy 13.4.6 Transition TDO(C) Drive Policy 13.4.7 Series TDO(C) Drive Policy components 13.4.7.1 Series System 13.4.7.2 Series Command 13.4.7.3 Series Control Level 13.4.8 Star-4 TDO(C) Drive Policies 13.4.8.1 Star-4 System 13.4.8.2 Star-4 Command 13.4.8.3 Star-4 control level 13.4.9 Hierarchical and flat views of the TDO(C) Drive Policy 13.4.10 Conceptual diagram of the TDO(C) Drive Policy 13.5 T0 TAP.7 TDOC Drive Policy 13.5.1 Description 13.5.2 Specifications 13.6 T1 and T2 TAP.7 TDOC Drive Policy 13.6.1 Description 13.6.2 Specifications 13.7 T3 and above TAP.7 TDOC Drive Policy 13.7.1 Description 13.7.2 Specifications 13.8 STL Group Membership 13.8.1 Tracking the Group Membership of STLs 13.8.2 STL Group Membership changes 13.8.2.1 Group membership changes with the Test-Logic-Reset state 13.8.2.2 Group membership changes with the Run-Test/Idle state 13.8.2.3 Group membership changes with the Pause-IR state 13.8.2.4 Group membership changes with the Pause-DR state 13.8.3 Commands/SSDs affecting group Scan Group Candidacy and Membership 13.8.3.1 Commands affecting Scan Group Candidacy 13.8.3.2 SSDs affecting Scan Group Candidacy and Membership 13.8.3.2.1 SSDs associated with the Run-Test/Idle state 13.8.3.2.2 SSDs associated with the Pause-IR state 13.8.3.2.3 SSDs associated with the Pause-DR state 13.8.4 Only Scan Group Member determination 13.8.4.1 Criteria 13.8.4.2 Method and information used to make determination 13.8.4.2.1 Idle Group Membership and membership counts 13.8.4.2.2 Pause-xR Group Membership and membership counts 13.8.4.2.3 Scan Group Membership and membership counts 13.8.4.2.4 Information recorded 13.8.5 STL group candidate and membership counts 13.8.5.1 Description 13.8.5.1.1 Scan Group Candidate Count (SGCC) 13.8.5.1.2 Potential Scan Group Membership Count Last 13.8.5.1.3 Factors creating SGCC and PSGMCL ambiguity 13.8.5.2 Specifications 13.8.6 Scan Group Membership Count Last determination 13.8.6.1 Description 13.8.6.2 Specification 13.8.7 Only Scan Group Member Last determination 13.8.7.1 Description 13.8.7.2 Specification 13.9 EPU Group Membership 13.9.1 Description 13.9.1.1 Tracking the EPU’s Group Membership 13.9.1.2 Conditional Group Member Count 13.9.1.3 Only Conditional Group Member determination 13.9.2 Specifications 13.10 Drive Policy summary 13.11 An approach to implementing TDOC Drive Policy 13.11.1 Policy generation 13.11.2 Potential Scan Group Member Last 13.11.3 The SGCC and PSGMCL functions 13.11.4 Determining Scan Group Only Member Last/Membership Count Last 13.11.5 The CGMC function 13.12 Programming considerations 14. TMS(C) Signal Drive Policy 14.1 Introduction 14.2 TMS(C) output bit types 14.2.1 Scan Packet content 14.2.2 Transport Packet content 14.2.3 Drive relationship with TCKC 14.3 Drive policy by output bit type 14.4 TMSC Signal Drive Types 14.4.1 TMSC Signal Drive Types 14.4.1.1 Single Drive 14.4.1.2 Joint Drive 14.4.1.3 Voting Drive 14.4.1.4 Inhibited Drive 14.4.2 Wire-ANDed TMSC signal values 14.5 Dormant Bit Drive Policy 14.5.1 Description 14.5.2 Specifications 14.6 Precharge Bit Drive Policy 14.6.1 Description 14.6.2 Specifications 14.7 RDY Bit Drive Policy 14.7.1 Description 14.7.1.1 Characteristics 14.7.1.2 Policy details 14.7.1.3 Relationship to CLTAPC selection state changes 14.7.2 Specifications 14.8 TDO Bit Drive Policy 14.8.1 Description 14.8.1.1 Characteristics 14.8.1.1.1 Policy details for System Path 14.8.1.1.2 Policy details for Control Path 14.8.1.2 Correlation to TDO(C) Drive Policy 14.8.1.3 Combined TDO bit drive summary 14.8.2 Specifications 14.9 Transport Bit Drive Policy 14.9.1 Description 14.9.2 Specifications 14.10 An approach to implementing TMSC Drive Policy 14.11 Programming considerations 15. IEEE 1149.1-compliance concepts 15.1 Introduction 15.2 Background 15.3 Test and debug views of a system of interest 15.4 An approach to implementing EMTAPC selection/deselection 16. T0 TAP.7 16.1 Introduction 16.2 Deployment 16.3 Capabilities 16.4 Configurations 16.4.1 Description 16.4.2 Specifications 16.5 Start-up behavior 16.5.1 Description 16.5.2 Specifications 16.6 Supporting multiple on-chip TAPCs 16.7 Controlling the selection state of EMTAPCs 16.7.1 Description 16.7.2 Specifications 16.8 Control via the CLTAPC Instruction Register 16.8.1 Description 16.8.1.1 Exclusion of TAPCs 16.8.1.2 Isolation of TAPCs 16.8.1.3 CLTAPC output registering of MTCP and MTDP control 16.8.2 Specifications 16.9 Control via one or more CLTAPC Data Registers 16.9.1 Description 16.9.2 Specifications 16.10 Control via internal or external tapc_select signals 16.10.1 Description 16.10.2 Specifications 16.11 Example use cases 16.11.1 IR control method with exclusions of TAPCs 16.11.2 IR control method with isolation of TAPCs 16.11.3 DR control method with exclusion of TAPCs 16.11.4 DR control method with isolation of TAPCs 16.12 Identification of on-chip TAP controller(s) 16.12.1 Description 16.12.2 Specifications 16.13 Multiple dies in one package 16.13.1 Description 16.13.1.1 Exposing an IEEE 1149.1 DR for the BYPASS and IDCODE instructions 16.13.1.2 Exposing the complete boundary-scan chain for IEEE 1149.1 instructions 16.13.1.3 BSDL documentation 16.13.1.4 Packaging dies 16.13.1.5 SiP-TAP POR* functionality 16.13.1.6 DR-wire bypass 16.13.2 Specifications 16.14 Managing STL Group Membership 16.15 RSU operation 16.15.1 Description 16.15.2 Specifications 16.16 Programming considerations 17. Extended concepts 17.1 Introduction 17.2 Suitability of BYPASS and IDCODE instructions for extended control 17.3 ZBS detection 17.3.1 Description 17.3.2 Specifications 17.4 Incrementing, locking, and clearing the ZBS count 17.4.1 Description 17.4.2 Specifications 17.5 Shared use of ZBSs by the EPU and STL 17.5.1 Description 17.5.1.1 EPU Operating States 17.5.1.2 EPU Operating State characteristics 17.5.1.3 ZBS use that is compatible with EPU Operating States 17.5.1.4 An approach to implementing EPU Operating States 17.5.2 Specifications 17.6 EPU functionality associated with the ZBS count 17.6.1 Description 17.6.2 Specifications 17.7 Programming considerations 18. T1 TAP.7 18.1 Introduction 18.2 Deployment 18.3 Capabilities 18.3.1 Inherited 18.3.2 New 18.4 Register and command portfolio 18.4.1 Description 18.4.1.1 General information 18.4.1.2 Register acronyms 18.4.1.3 Global Registers 18.4.1.4 Registers already described 18.4.1.5 New register descriptions 18.4.2 Specifications 18.5 Configurations 18.5.1 Description 18.5.2 Specifications 18.6 Start-up behavior 18.6.1 Description 18.6.2 Specifications 18.7 Conditional Group Membership 18.8 Test Reset 18.8.1 Description 18.8.2 Specifications 18.9 Functional reset 18.9.1 Description 18.9.2 Specifications 18.10 Power control 18.10.1 Description 18.10.1.1 Overview 18.10.1.1.1 Use cases 18.10.1.1.2 Power-control options 18.10.1.1.3 Power management within a typical system 18.10.1.1.4 Power-control topics 18.10.1.2 Power-Control Model 18.10.1.2.1 TAP.7 Controller power-management states 18.10.1.2.2 Key model attributes 18.10.1.3 The chip-level power manager’s role in power control 18.10.1.3.1 Responsibilities 18.10.1.3.2 Interaction with TAP.7 Controller 18.10.1.3.3 Periods when a Type-0 Reset is asserted 18.10.1.3.4 Handling of power-up and power-down requests 18.10.1.3.5 Chip-Level power-up and power-down enables 18.10.1.3.6 The default Power-Control Mode 18.10.1.4 The DTS’ role in power control 18.10.1.4.1 Responsibilities 18.10.1.4.2 Directed power-up 18.10.1.4.3 Detected power-up 18.10.1.5 The TAP.7 Controller’s role in power control 18.10.1.5.1 Responsibilities 18.10.1.5.2 Operation 18.10.1.5.3 Test periods 18.10.1.5.4 Power-up confirmation test 18.10.1.5.5 Power-down initiation test 18.10.1.5.6 Power-down request summary 18.10.1.5.7 Awaiting power-down with the TAP.7 Controller operation shutdown 18.10.1.6 Example power-down sequences 18.10.1.7 An approach to implementing power control 18.10.2 Specifications 18.11 RSU operation 18.11.1 Description 18.11.2 Specifications 18.12 Programming considerations 19. T2 TAP.7 19.1 Introduction 19.2 Deployment 19.3 Capabilities 19.3.1 Inherited 19.3.2 New 19.4 Register and command portfolio 19.4.1 Description 19.4.1.1 General information 19.4.1.2 Register acronyms 19.4.1.3 Effects of a Long-Form Selection Sequence 19.4.1.4 New register descriptions 19.4.2 Specifications 19.5 Configurations 19.5.1 Description 19.5.2 Specifications 19.6 Start-up behavior 19.6.1 Description 19.6.2 Specifications 19.7 Scan formats 19.7.1 Description 19.7.2 Specifications 19.8 STL Group Membership 19.8.1 Description 19.8.1.1 Factors affecting group membership 19.8.1.2 Reset effects 19.8.1.3 TAPC state effects 19.8.1.4 Control Path effects 19.8.1.5 Parked state/selection relationships 19.8.1.6 Concurrent CLTAPC and EMTAPC selection changes 19.8.1.7 An approach to implementing CLTAPC selection with the T2 Class 19.8.2 Specifications 19.9 RSU operation 19.9.1 Description 19.9.2 Specifications 19.10 Programming considerations 20. T3 TAP.7 20.1 Introduction 20.2 Deployment 20.3 Capabilities 20.3.1 Inherited 20.3.2 New 20.4 Register and command portfolio 20.4.1 Description 20.4.1.1 General information 20.4.1.2 Register acronyms 20.4.1.3 Effect of a Long-Form Selection Sequence 20.4.2 Specifications 20.5 Configurations 20.5.1 Description 20.5.2 Specifications 20.6 Start-up behavior 20.6.1 Description 20.6.2 Specifications 20.7 Scan formats 20.7.1 Description 20.7.2 Specifications 20.8 TAP.7 Controller Address (TCA) 20.8.1 Description 20.8.2 Specifications 20.9 Aliasing the TCA to a Controller ID 20.9.1 Description 20.9.1.1 CID Allocate Command (CIDA) 20.9.1.1.1 CID-allocation criteria 20.9.1.1.2 CID-allocation candidates 20.9.1.1.3 CID-allocation process 20.9.1.1.4 Directed CID Allocation 20.9.1.1.5 Undirected CID Allocation 20.9.1.2 External AT generation with the JScan3 Scan Format 20.9.1.3 CID-allocation examples 20.9.1.4 An approach to implementing CID allocation 20.9.2 Specifications 20.10 Scan Selection Directives 20.10.1 Description 20.10.1.1 Overview 20.10.1.2 SSD format 20.10.1.3 SSD effects on STL Group Membership 20.10.1.4 Enabling SSD processing 20.10.1.5 SSD processing 20.10.1.6 Conditional SSD execution 20.10.1.7 SSD interaction with other controller functions 20.10.1.8 SSD State Machine 20.10.1.9 SSD states allowing Scan Group Membership 20.10.1.9.1 Using SSDs to create Series and Star-Equivalent Scans 20.10.1.9.2 Examples of SSD use 20.10.1.10 An approach to implementing the SSD function 20.10.2 Specifications 20.11 Scan Topology Training Sequence 20.11.1 Description 20.11.1.1 Overview 20.11.1.2 Topology Register Function 20.11.1.3 Use cases 20.11.1.3.1 Operation with a single TAP.7 Branch 20.11.1.3.2 Operation with more than one TAP.7 Branch 20.11.1.4 Scan-path characteristics used to determine the scan topology 20.11.1.5 Scan Topology Training Command Sequence 20.11.1.5.1 Connectivity test 20.11.1.5.2 Continuity test 20.11.2 Specifications 20.12 Managing STL Group Membership 20.12.1 Description 20.12.1.1 Factors affecting group membership 20.12.1.2 An approach to implementing CLTAPC selection with T3 and above classes 20.12.2 Specifications 20.13 RSU operation 20.13.1 Description 20.13.2 Specifications 20.14 Programming considerations 21. Advanced concepts 21.1 Architecture 21.2 Advanced capabilities 21.2.1 Mandatory and optional capabilities 21.2.2 Online and Offline operation 21.2.3 Interoperability with T0–T3 TAP.7s 21.2.4 Interoperability with T4 and above TAP.7s 21.3 Comparing the Standard and Advanced Protocols 21.4 APU functions 21.4.1 Conceptual view 21.4.2 Bypass Function 21.4.3 Scan Function 21.4.4 Transport Function 21.4.5 Bypass/Scan/Control Function interactions 21.5 APU interfaces 21.5.1 TAP 21.5.2 EPU 21.5.3 DCC 21.6 APU function/Operating State relationships 21.6.1 Operating State/function relationships 21.6.2 APU Operating State changes 21.6.3 Example operating state sequences 21.7 TAPC state/packet relationships 21.7.1 TAPC state and packet sequence relationships 21.7.2 Constructing packet sequences 21.7.3 Packet combinations/TAPC state relationships 21.7.4 Scheduling of packets 21.8 User’s and implementer’s views of the Advanced Protocol 21.8.1 User’s view 21.8.2 Implementer’s view 21.9 An approach to implementing APU Operating State scheduling 21.10 Structure of the clauses describing T4 and above TAP.7s 22. APU Scan Packets 22.1 CPs 22.2 SPs 22.2.1 Conceptual view of an SP 22.2.2 SP format 22.2.3 SP content 22.2.3.1 Header Element content 22.2.3.2 Payload Element content 22.2.3.3 Delay Element content 22.2.4 Types of output bit-frame transactions 22.3 SPs that advance the TAPC state 22.4 TPs 22.4.1 Conceptual view of a TP 22.4.2 TP format 22.4.3 Content 22.5 APU state diagram 22.6 An approach to implementing packet scheduling 22.6.1 Pipelining and its effects 22.6.2 SP Element scheduling 22.6.3 TP Element scheduling 23. T4 TAP.7 23.1 Introduction 23.2 Deployment 23.3 Capabilities 23.3.1 Inherited 23.3.2 New 23.4 Register and command portfolio 23.4.1 Description 23.4.1.1 General information 23.4.1.2 Register acronyms 23.4.1.3 Effect of a Long-Form Selection Sequence 23.4.1.4 New register descriptions 23.4.1.4.1 Auxiliary Pin Function Control (APFC) Register 23.4.1.4.2 Delay Control (DLYC) Register 23.4.1.4.3 Ready Control (RDYC) Register 23.4.1.4.4 Sample Using Rising Edge (SREDGE) Register 23.4.1.4.5 Scan Format (SCNFMT) Register 23.4.1.4.6 System Test Clock Duty Cycle (STCKDC) Register 23.4.2 Specifications 23.5 Configurations 23.5.1 Description 23.5.2 Specifications 23.6 Start-up behavior 23.6.1 Description 23.6.2 Specifications 23.7 Scan formats 23.7.1 Description 23.7.1.1 Overview 23.7.1.2 Addition of optional scan formats 23.7.1.3 Influences on scan format definition 23.7.1.4 Performance and flexibility tradeoffs 23.7.1.5 Comparing the scan formats 23.7.1.5.1 MScan 23.7.1.5.2 OScan 23.7.1.5.3 SScan 23.7.2 Specification 23.8 Configuration Faults 23.8.1 Description 23.8.2 Specifications 23.9 Increasing STL performance 23.9.1 Description 23.9.2 Specifications 23.10 Auxiliary Pin Function Control 23.10.1 Description 23.10.2 Specifications 23.11 Sample Using Rising Edge 23.11.1 Description 23.11.2 Specifications 23.12 System and EPU TMS signal values 23.12.1 Description 23.12.2 Specifications 23.13 System and EPU TDI signal values 23.13.1 Description 23.13.2 Specifications 23.14 RDY bit values 23.14.1 Description 23.14.2 Specifications 23.15 TDO bit values 23.15.1 Description 23.15.2 Specifications 23.16 Advanced Protocol effects on the EPU/CLTAPC relationship 23.16.1 Description 23.16.2 Specifications 23.17 SSD detection 23.17.1 Description 23.17.2 Specifications 23.18 Programming considerations 23.19 An approach to implementing a TAP.7 Controller with maximum performance 24. MScan Scan Format 24.1 Capabilities 24.1.1 Primary purpose 24.1.2 Application types supported 24.1.3 Important characteristics 24.2 High-level operation 24.3 Scan Packet content 24.3.1 Description 24.3.2 Specifications 24.4 Payload Element 24.4.1 Description 24.4.1.1 Format 24.4.1.2 Relationship to EPU signals 24.4.1.3 RDY bits 24.4.2 Specification 24.5 Delay Element 24.5.1 Description 24.5.1.1 Format 24.5.1.2 Delay Element Directives 24.5.1.3 Uses 24.5.2 Specifications 24.6 Advancing the TAPC state 24.6.1 Description 24.6.2 Specifications 24.7 CID allocation 24.7.1 Description 24.7.2 Specifications 24.8 Increasing STL performance with the MScan Scan Format 24.9 An approach to implementing the MScan Scan Format 24.9.1 Payload State Machine 24.9.2 Ready State Machine 24.9.3 Delay State Machine 24.10 Where to find examples 25. OScan Scan Formats 25.1 Capabilities 25.1.1 Primary purpose 25.1.2 Application types supported 25.1.3 Important characteristics 25.2 High-level operation 25.3 Scan Packet content 25.3.1 Description 25.3.2 Specifications 25.4 Payload Element 25.4.1 Description 25.4.1.1 Format 25.4.1.2 Optimizations 25.4.1.3 Relationship to EPU signals 25.4.1.4 Input bit-frame 25.4.1.5 Drive types 25.4.1.6 RDY bits 25.4.2 Specifications 25.5 Delay Element 25.6 Advancing the TAPC state 25.6.1 Description 25.6.2 Specifications 25.7 CID allocation 25.7.1 Description 25.7.2 Specifications 25.8 Increasing STL performance with OScan Scan Formats 25.9 An approach to implementing OScan Scan Formats 25.9.1 Payload State Machine 25.9.2 Shift Progress flag 25.9.3 CSM and SSM activation 25.9.4 RDY State Machine 25.9.5 TAP advance 25.10 Where to find examples 26. SScan Scan Formats 26.1 Capabilities 26.1.1 Primary purpose 26.1.2 Application types supported 26.1.3 Control Segments 26.1.4 Data Segments 26.1.5 Stall profiles 26.1.6 Important characteristics 26.2 High-level operation 26.2.1 Overview 26.2.2 Segments and their use 26.2.2.1 Description 26.2.2.1.1 Use with a TAP.1-like component 26.2.2.1.2 Use with a DMA or FIFO component 26.2.2.1.3 Use with a direct-access data-rate-dependent component 26.2.2.1.4 Use with a buffered TDI/TMS component 26.2.2.1.5 Utilizing the same scan format for two applications types 26.2.2.2 Specifications 26.3 Scan Packet content 26.3.1 Description 26.3.2 Specifications 26.4 Header Element 26.4.1 Description 26.4.2 Specifications 26.5 Payload Element 26.5.1 Description 26.5.1.1 Factors determining payload content 26.5.1.2 Optimizations 26.5.1.3 Input bit-frame 26.5.1.4 Output bit-frame 26.5.1.4.1 Content 26.5.1.4.2 SScan0/1 output-only segments 26.5.1.4.3 SScan2/3 output-only segments 26.5.2 Specifications 26.6 Delay Element 26.7 Packet sequences and factors influencing them 26.7.1 Description 26.7.2 Specifications 26.8 Advancing the TAPC state 26.8.1 Description 26.8.1.1 SP followed by a CP 26.8.1.2 Control Segments 26.8.1.3 Data Segments 26.8.2 Specifications 26.9 CID allocation 26.9.1 Description 26.9.2 Specifications 26.10 Increasing STL performance with SScan Scan Formats 26.11 An approach to implementing SScan Scan Formats 26.11.1 Payload State Machine 26.11.2 Escape Detection State Machine 26.11.3 Shift Progress flag 26.11.4 TAP advance 26.11.5 Additional entry point loads for output-only segments 26.11.6 Header Register 26.11.7 Timing diagrams 26.12 Where to find examples 27. T5 TAP.7 27.1 Introduction 27.2 Deployment 27.3 Capabilities 27.3.1 Inherited 27.3.2 New 27.4 Register and command portfolio 27.4.1 Description 27.4.1.1 General information 27.4.1.2 Register acronyms 27.4.1.3 Effect of a Long-Form Selection Sequence 27.4.1.4 Transport protocol revision (TPPREV) register 27.4.1.5 Transport states (TPST) 27.4.1.6 Data Element length (TP_DELN) 27.4.1.7 Physical Data Channel to Logical Data Channel association (PDCx_LCA) 27.4.1.8 Physical Data Channel selected (PDCx_SEL) 27.4.1.9 Physical Data Channel DCC selection (PDCx_DCC) 27.4.1.10 Physical Data Channel DCC Control Registers (PDCx_DCCy_CRz) 27.4.2 Specifications 27.5 Configurations 27.5.1 Description 27.5.2 Specifications 27.6 Start-up behavior 27.6.1 Description 27.6.2 Specifications 27.7 Configuration Faults 27.7.1 Description 27.7.2 Specifications 27.8 Enabling transport 27.8.1 Description 27.8.2 Specifications 27.9 Transport Packet composition 27.9.1 Operations 27.9.2 Directive, Register, and Data Elements 27.10 Directive Elements 27.10.1 Description 27.10.1.1 Overview 27.10.1.2 Directive Element acronyms 27.10.1.3 Surrounding context of directives 27.10.1.4 Directive/transport building block relationships 27.10.1.5 Directive encoding 27.10.1.6 Directive types 27.10.1.6.1 Unconditional Directives 27.10.1.6.2 Reset Directives 27.10.1.6.3 Selection Directives 27.10.1.6.4 Conditional Directives 27.10.1.6.5 Transfer Directives 27.10.2 Specifications 27.11 Register Elements 27.11.1 Description 27.11.1.1 Overview 27.11.1.2 Register Element length 27.11.1.3 Transfer direction 27.11.1.4 Summary of Register Element characteristics 27.11.2 Specifications 27.12 Data Elements 27.12.1 Description 27.12.1.1 Overview 27.12.1.2 Data Element length 27.12.1.3 Transfer direction 27.12.1.4 Utilization and generation of data 27.12.1.5 Operation with single and multiple clients 27.12.1.6 Summary of Data Element characteristics 27.12.2 Specifications 27.13 Selection of control and data targets 27.14 Data Channel Client functions 27.14.1 Description 27.14.1.1 Initializing a Data Channel Client 27.14.1.2 Orderly shutdown of a transfer 27.14.1.3 Effects of Online/Offline operation on the Transport Function 27.14.2 Specifications 27.15 Partitioning of the Transport Control Function 27.15.1 Building blocks 27.15.2 Directive/register/operational relationships 27.16 Programming considerations 27.16.1 Managing transport with the DTS 27.16.2 Single and multi-client data exchanges 27.16.3 Bandwidth allocation 27.16.4 Common and uncommon operations performed with directives 27.16.5 Dynamic source/destination changes 27.16.6 Transfer alignment characteristics 27.17 Aspects of transport not covered by this specification 28. Transport operation and interfaces 28.1 Introduction 28.2 TAP interface 28.2.1 TPA state flow 28.2.2 Directive Element characteristics 28.2.2.1 Description 28.2.2.2 Specifications 28.2.3 Register Element characteristics 28.2.3.1 Description 28.2.3.1.1 Format, timing, and TMSC signal drive characteristics 28.2.3.1.2 Register Element length 28.2.3.1.3 Register Element content 28.2.3.2 Specifications 28.2.4 Data Element characteristics 28.2.4.1 Description 28.2.4.1.1 Format, timing, and TMSC signal drive characteristics 28.2.4.1.2 Data Element length 28.2.4.1.3 Data Element content 28.2.4.1.4 Drive characteristics 28.2.4.1.5 Multi-client data transfers 28.2.4.1.6 Data Element alignment with the data that is transported 28.2.4.2 Specifications 28.3 Transport State Machine 28.3.1 Description 28.3.1.1 Conceptual view 28.3.1.2 TSM operation 28.3.1.3 Scheduling a TP 28.3.1.4 Starting/restarting directive processing 28.3.1.5 Completing a TP 28.3.2 Specifications 28.4 PDCx/DCC interface 28.4.1 Description 28.4.1.1 Signal functions 28.4.1.2 Signal descriptions 28.4.1.3 Signal use 28.4.2 Specifications 28.5 Five-bit directives 28.5.1 Description 28.5.2 Specifications 28.6 Eight-bit directives 28.6.1 Description 28.6.2 Specifications 28.7 12-bit directives 28.7.1 Description 28.7.2 Specifications 28.8 DCC interface operation 28.8.1 Basic capability 28.8.2 Pipelining register dcc_rdo signaling 28.8.3 Pipelining dcc_ddo and dcc_cor signaling 28.9 An approach to implementing the Transport Function 28.9.1 Overview 28.9.2 The Transport State Machine 28.9.3 Multi-use register bits 28.9.3.1 Input configurations 28.9.3.2 Transport Packet processing 28.9.3.2.1 Directive processing 28.9.3.2.2 Data Element processing 28.9.3.2.3 12-bit directive processing (other than TP_CRR and TP_CRW) 28.9.3.2.4 TP_CRR and TP_CRW Directive processing 28.9.3.3 TSM state/register value relationships 28.9.3.4 Transport output and DCR input selection 28.9.3.5 TP activity examples 29. Test concepts 29.1 Introduction 29.2 Interoperability 29.3 Construction of the unit under test 29.4 Background (IEEE 1149.1 paradigm) 29.4.1 Topology 29.4.2 Scan-state sequencing 29.5 Implications for test applications arising from this standard 29.5.1 Divergences versus IEEE Std 1149.1 29.5.2 Accommodation/resolution of divergences versus IEEE Std 1149.1 29.6 Test example—a narrative 29.7 Describing the unit under test 29.8 Documentation model 29.9 Considerations for large-system applications 30. Documenting IEEE 1149.7 test endpoints (BSDL.7) 30.1 Introduction 30.2 Conventions 30.3 Purpose of BSDL.7 30.4 Scope of BSDL.7 30.5 Expectations of a BSDL.7 parser 30.6 Relationship of BSDL.7 to BSDL.1 30.6.1 Description 30.6.2 Specifications 30.7 Lexical elements of BSDL.7 30.7.1 Description 30.7.2 Specifications 30.8 BSDL.7 reserved words 30.8.1 Description 30.8.2 Specifications 30.9 Components of a BSDL.7 description 30.9.1 Description 30.9.2 Specifications 30.10 The entity description (BSDL.7) 30.10.1 Overall structure of the entity description (BSDL.7) 30.10.1.1 Syntax and content 30.10.1.1.1 Description 30.10.1.1.2 Specifications 30.10.1.2 Semantic checks 30.10.1.2.1 Description 30.10.1.2.2 Specifications 30.10.2 Standard use statement (BSDL.7) 30.10.2.1 Syntax and content 30.10.2.1.1 Description 30.10.2.1.2 Specifications 30.10.2.2 Examples 30.10.3 Version control 30.10.3.1 Syntax and content 30.10.3.1.1 Description 30.10.3.1.2 Specifications 30.10.4 Component conformance statement (BSDL.7) 30.10.4.1 Syntax and content 30.10.4.1.1 Description 30.10.4.1.2 Specifications 30.10.4.2 Examples 30.10.4.3 Semantic checks 30.10.5 Scan port identification (BSDL.7) 30.10.5.1 Syntax and content 30.10.5.1.1 Description 30.10.5.1.2 Specifications 30.10.5.2 Examples 30.10.5.3 Semantic checks 30.10.5.3.1 Description 30.10.5.3.2 Specifications 30.10.6 Compliance enable description (BSDL.7) 30.10.6.1 Syntax and content 30.10.6.1.1 Description 30.10.6.1.2 Specifications 30.10.6.2 Examples 30.10.6.3 Semantic checks 30.10.6.3.1 Description 30.10.6.3.2 Specifications 30.10.7 Device identification register description (BSDL.7) 30.10.7.1 Syntax and content 30.10.7.1.1 Description 30.10.7.1.2 Specifications 30.10.7.2 Examples 30.10.7.3 Semantic checks 30.10.7.3.1 Description 30.10.7.3.2 Specifications 30.10.8 Configuration register description (BSDL.7) 30.10.8.1 Syntax and content 30.10.8.1.1 Description 30.10.8.1.2 Specifications 30.10.8.2 Examples 30.10.8.3 Semantic checks 30.10.8.3.1 Description 30.10.8.3.2 Specifications 30.11 The Standard BSDL.7 Package STD_1149_7_2009 30.11.1 Description 30.11.2 Specifications 30.12 A typical application of BSDL.7 31. Documenting IEEE 1149.7 test modules (HSDL.7) 31.1 Introduction 31.2 Conventions 31.3 Purpose of HSDL.7 31.4 Scope of HSDL.7 31.5 Expectations of an HSDL.7 parser 31.6 Relationship of HSDL.7 to BSDL.7 (and BSDL.1) 31.6.1 Description 31.6.2 Specifications 31.7 Lexical elements of HSDL.7 31.7.1 Description 31.7.2 Specifications 31.8 HSDL.7 reserved words 31.8.1 Description 31.8.2 Specifications 31.9 Components of an HSDL.7 description 31.9.1 Description 31.9.2 Specifications 31.10 The entity description (HSDL.7) 31.10.1 Overall structure of the entity description (HSDL.7) 31.10.1.1 Syntax and content 31.10.1.1.1 Description 31.10.1.1.2 Specifications 31.10.1.2 Semantic checks 31.10.1.2.1 Description 31.10.1.2.2 Specifications 31.10.2 Module standard use statement (HSDL.7) 31.10.2.1 Syntax and content 31.10.2.1.1 Description 31.10.2.1.2 Specifications 31.10.2.2 Examples 31.10.3 Version control 31.10.3.1 Syntax and content 31.10.3.1.1 Description 31.10.3.1.2 Specifications 31.10.4 Module component conformance statement (HSDL.7) 31.10.4.1 Syntax and content 31.10.4.1.1 Description 31.10.4.1.2 Specifications 31.10.4.2 Examples 31.10.4.3 Semantic checks 31.10.5 Module package pin mappings (HSDL.7) 31.10.5.1 Syntax and content 31.10.5.1.1 Description 31.10.5.1.2 Specifications 31.10.5.2 Examples 31.10.5.3 Semantic checks 31.10.5.3.1 Description 31.10.5.3.2 Specifications 31.10.6 Module scan port identification (HSDL.7) 31.10.6.1 Syntax and content 31.10.6.1.1 Description 31.10.6.1.2 Specifications 31.10.6.2 Examples 31.10.6.3 Semantic checks 31.10.6.3.1 Description 31.10.6.3.2 Specifications 31.10.7 Module members declaration (HSDL.7) 31.10.7.1 Syntax and content 31.10.7.1.1 Description 31.10.7.1.2 Specifications 31.10.7.2 Examples 31.10.7.3 Semantic checks 31.10.7.3.1 Description 31.10.7.3.2 Specifications 31.11 The Standard HSDL.7 Package STD_1149_7_2009_module 31.11.1 Description 31.11.2 Specifications 31.12 Applications of HSDL.7 31.12.1 HSDL.7 for IEEE 1149.1 serial connection using one TMS signal 31.12.2 HSDL.7 for IEEE 1149.1 connection in two paralleled serial chains 31.12.3 HSDL.7 for a basic Star Scan Topology 31.12.4 HSDL.7 for a basic hierarchical topology 31.12.5 A typical application of HSDL.7 Annex A (informative) IEEE 1149.1 reference material Annex B (informative) Scan examples in timing diagram form B.1 MScan and OScan SP types B.2 MScan and OScan transactions B.2.1 MScan transaction B.2.2 OScan0 transaction B.2.3 OScan1 transaction B.2.4 OScan2 transaction B.2.5 OScan3 transaction B.2.6 OScan4 transaction B.2.7 OScan5 transaction B.2.8 OScan6 transaction B.2.9 OScan7 transaction B.3 SScan transactions B.3.1 SScan0 transaction B.3.2 SScan1 transaction B.3.3 SScan2 transaction B.3.4 SScan3 transaction B.4 BDX and CDX Transport Packet examples Annex C (informative) Scan examples in tabular form C.1 Overview C.2 MScan and OScan SP types C.3 SScan SP types Annex D (informative) Programming considerations D.1 Overview D.2 DTS’ view of TAPs D.2.1 Technology branches D.2.2 Power-management RSU combinations D.2.3 TAP.7 Controller deselection and selection D.2.4 Start-up versus steady-state operation D.2.5 Start-up D.2.6 Initialization requirements D.2.6.1 Initial state D.2.6.2 Factors influencing initialization D.2.6.3 Initialization function D.2.6.4 Reset Escape D.2.6.5 Reset TAP.7 Controllers without an RSU D.2.6.6 Power-up TAP.7 Controllers that are un-powered D.2.6.7 Placing a TAP.7 Controller Online that is Offline-at-Start-up D.2.7 Scan Topology Training D.3 Scan topology interrogation D.3.1 Series Branch interrogation D.3.1.1 Series characteristics used for interrogation D.3.1.2 Interrogation process D.3.1.3 Configuration Register reads D.3.1.4 Determining whether a Series Branch is selectable D.3.1.5 Quick determination of TAP types in a Series Branch D.3.2 Star-4 Branch interrogation D.3.2.1 Information provided D.3.2.2 Interrogation process D.3.3 Star-2 Branch interrogation D.3.3.1 Information provided D.3.3.2 Interrogation process D.4 Establishing TAP.7 operating conditions D.5 CID management D.6 Managing simultaneous debug actions D.7 Operations to avoid with a Star-4 Scan Topology D.7.1 The use of the JScan0–JScan2 Scan Formats D.7.2 The selection of CLTAPCs of TAP.7 Controllers allocated the same CID D.8 Using a T5 TAP.7 D.8.1 Setup and use of the Transport Function D.8.2 Sharing the use of a Logical Data Channel D.8.3 Transferring data with Transport Packet Data Payloads Annex E (informative) Recommended electrical characteristics Annex F (informative) Connectivity/electrical recommendations F.1 Overview F.1.1 General information F.1.2 Factors affecting reliable operation F.1.3 Factors affecting link performance F.2 Physical connection topologies considered F.3 Termination schemes considered F.4 Chip considerations F.4.1 SOC input conditioning F.4.2 Signal driver rise and fall times F.4.3 Clock-to-output delays F.4.4 Supply and buffer impedances F.4.5 Additional chip considerations related to multi-TAPC topologies F.5 Board considerations F.5.1 Signaling requiring a termination scheme F.5.1.1 Lumped load F.5.1.2 Distributed load F.5.1.3 Classifying a load F.5.1.4 Transmission-line impedance F.5.2 Impedance discontinuities/symmetry F.5.3 Transmission-line construction F.5.3.1 Uniformity of transmission-line impedance F.5.3.2 Proper construction F.5.3.3 Improper construction F.5.3.4 Connector treatment F.5.4 Choosing a connection configuration F.5.5 Termination schemes with simple configurations F.5.5.1 Series termination F.5.5.1.1 Overview F.5.5.1.2 Challenges in series termination F.5.5.1.3 Benefits of using series termination F.5.5.2 Parallel termination F.5.5.2.1 Overview F.5.5.2.2 Challenges in using parallel termination F.5.5.2.3 Benefits of using parallel termination F.5.5.3 Parallel AC termination F.5.5.3.1 Overview F.5.5.3.2 Challenges in using parallel AC termination F.5.5.3.3 Benefits of using parallel AC termination F.5.6 Effects of transmission-line length on operating frequency F.5.7 Capacitive load isolation and input pin low-pass filtering F.5.8 DTS and chip models F.5.9 Additional board considerations related to multi-TAPC topologies F.6 System considerations for supporting Keeper bias (K bias) in multi-TAPC topologies F.6.1 K bias considerations at the chip and board level F.6.2 K bias considerations for embedded TAPC topologies F.7 DTS considerations F.7.1 Source impedance F.7.2 Input capacitance isolation F.7.2.1 DTS output levels with parallel terminated target topologies F.7.2.2 DTS output edge rates F.7.2.3 High-speed, high-current, low-voltage configurable edge-rate drivers F.7.2.4 Low-voltage, high-current fixed slow edge-rate drive translator F.7.2.5 In-system DTS considerations F.7.2.5.1 Output buffer impedance F.7.2.5.2 Power considerations F.7.2.5.3 Signal edge rates F.8 Point-to-Point configuration F.8.1 Model F.8.2 Unidirectional signaling F.8.2.1 Series termination F.8.2.2 Parallel AC termination F.8.3 Bidirectional signaling F.9 Line configuration of a transmission line F.9.1 Model F.9.2 Unidirectional signaling F.9.2.1 Parallel AC termination F.9.2.2 Parallel termination F.9.2.3 Summary F.9.3 Bidirectional signaling F.9.3.1 Four loads F.9.3.2 Eight loads F.10 T configuration of a transmission line F.10.1 Model F.10.2 Unidirectional signaling F.10.3 Bidirectional signaling F.11 X configuration of a transmission line F.11.1 Model F.11.2 Unidirectional signaling F.11.3 Bidirectional signaling F.12 XT configuration of a transmission line F.12.1 Model F.12.2 Unidirectional signaling F.12.3 Bidirectional signaling F.13 Recommendations F.13.1 Summary F.13.2 Connectivity/termination scheme F.13.3 Termination scheme/capacitive load isolation/signal relationships F.13.4 Utilizing board design tools and simulation Annex G (informative) Utilizing SScan Scan Formats Annex H (informative) The RTCK signal Annex I (informative) Bibliography Index