ENGLISH

Handbook of algorithms for physical design automation

By Sachin S. Sapatnekar; Charles J. Alpert; Dinesh P. Mehta (eds.)

Book information

Publisher
Auerbach Publications
Year
2009
ISBN
9780849372421, 0849372429, 9781420013481, 1420013483
Language
english
Format
PDF
Filesize
20 MB (21397007 bytes)
Pages
\1044
Time added
2021-12-05 23:14:26

Description

Front cover Contents Editors Contributors Part I: Introduction Chapter 1. Introduction to Physical Design Chapter 2. Layout Synthesis: A Retrospective Chapter 3. Metrics Used in Physical Design Part II: Foundations Chapter 4. Basic Data Structures Chapter 5. Basic Algorithmic Techniques Chapter 6. Optimization Techniques for Circuit Design Applications Chapter 7. Partitioning and Clustering Part III: Floorplanning Chapter 8. Floorplanning: Early Research Chapter 9. Slicing Floorplans Chapter 10. Floorplan Representations Chapter 11. Packing Floorplan Representations Chapter 12. Recent Advances in Floorplanning Chapter 13. Industrial Floorplanning and Prototyping Part IV: Placement Chapter 14. Placement: Introduction/ Problem Formulation Chapter 15. Partitioning-Based Methods Chapter 16. Placement Using Simulated Annealing Chapter 17. Analytical Methods in Placement Chapter 18. Force-Directed and Other Continuous Placement Methods Chapter 19. Enhancing Placement with Multilevel Techniques Chapter 20. Legalization and Detailed Placement Chapter 21. Timing-Driven Placement Chapter 22. Congestion-Driven Physical Design Part V: Net Layout and Optimization Chapter 23. Global Routing Formulation and Maze Routing Chapter 24. Minimum Steiner Tree Construction* Chapter 25. Timing-Driven Interconnect Synthesis Chapter 26. Buffer Insertion Basics Chapter 27. Generalized Buffer Insertion Chapter 28. Buffering in the Layout Environment Chapter 29. Wire Sizing Part VI: Routing Multiple Signal Nets Chapter 30. Estimation of Routing Congestion Chapter 31. Rip-Up and Reroute Chapter 32. Optimization Techniques in Routing Chapter 33. Global Interconnect Planning Chapter 34. Coupling Noise Part VII: Manufacturability and Detailed Routing Chapter 35. Modeling and Computational Lithography Chapter 36. CMP Fill Synthesis: A Survey of Recent Studies Chapter 37. Yield Analysis and Optimization Chapter 38. Manufacturability-Aware Routing Part VIII: Physical Synthesis Chapter 39. Placement-Driven Synthesis Design Closure Tool Chapter 40. X Architecture Place and Route: Physical Design for the X Interconnect Architecture Part IX: Designing Large Global Nets Chapter 41. Inductance Effects in Global Nets Chapter 42. Clock Network Design: Basics Chapter 43. Practical Issues in Clock Network Design Chapter 44. Power Grid Design Part X: Physical Design for Specialized Technologies Chapter 45. Field-Programmable Gate Array Architectures Chapter 46. FPGA Technology Mapping, Placement, and Routing Chapter 47. Physical Design for Three-Dimensional Circuits Index Back cover

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