ENGLISH

Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)

By Zeljko Zilic , Katarzyna Radecka

Book information

Year
2003
ISBN
1402076525, 9781402076527, 9780306487392
LCC
TK7874.75 .R33 2003
Open Library ID
OL19290691M
Language
english
Format
PDF
Filesize
8 MB (8146096 bytes)
Edition
1
Pages
233\233
Scanned
yes
Time added
2011-06-04 13:46:07

Description

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

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