Fundamentals of Digital and Computer Design with VHDL

Description

This text is intended for an introductory digital design course for students at the freshman level; it also is intended for an introductory computer design course with assembly language programming for students at the sophomore level. This text uses a spiral teaching approach by introducing a design problem and then, in the same chapter or a later chapter, either (1) reemphasizing the same concepts when a different design is presented, or (2) working the same problem using a different technique. This is done to increase the likelihood of retention. Title Contents 1 Boolean Algebra, Boolean Functions, VHDL, and Gates 1.1 Introduction 1.2 Basics of Boolean Algebra 1.2.1 Venn Diagrams 1.2.2 Black Boxes for Boolean Functions 1.2.3 Basic Logic Symbols 1.2.4 Boolean Algebra Postulates 1.2.5 Boolean Algebra Theorems 1.2.6 Proving Boolean Algebra Theorems 1.3 Deriving Boolean Functions from Truth Tables 1.3.1 Deriving Boolean Functions Using the 1s of the Functions 1.3.2 Deriving Boolean Functions Using the 0s of the Functions 1.3.3 Deriving Boolean Functions Using Minterms and Maxterms 1.4 Writing VHDL Designs for Simple Gate Functions 1.4.1 VHDL Design for a NOT Function 1.4.2 VHDL Design for an AND Function 1.4.3 VHDL Design for an OR Function 1.4.4 VHDL Design for an XOR Function 1.4.5 VHDL Design for a NAND Function 1.4.6 VHDL Design for a NOR Function 1.4.7 VHDL Design for an XNOR Function 1.4.8 VHDL Design for a BUFFER Function 1.4.9 VHDL Design for any Boolean Function Written in Canonical Form 1.5 More about Logic Gates 1.5.1 Equivalent Gate Symbols 1.5.2 Functionally Complete Gates 1.5.3 Equivalent Gate Circuits 1.5.4 Compact Description Names for Gates 1.5.5 International Logic Symbols for Gates Problems 2 Number Conversions, Codes, and Function Minimization 2.1 Introduction 2.2 Digital Circuits versus Analog Circuits 2.2.1 Digitized Signal for the Human Heart 2.2.2 Discrete Signals versus Continuous Signals 2.3 Binary Number Conversions 2.3.1 Decimal, Binary, Octal, and Hexadecimal Numbers 2.3.2 Conversion Techniques 2.4 Binary Codes 2.4.1 Minimum Number of Bits for Keypads and Keyboards 2.4.2 Commonly Used Codes: BCD, ASCII, and Others 2.4.3 Modulo-2 Addition and Conversions between Binary and Refl ective Gray Code 2.4.4 7-Segment Code 2.4.5 VHDL Design for a Letter Display System 2.5 Karnaugh Map Reduction Method 2.5.1 The Karnaugh Map Explorer 2.5.2 Using a 2-Variable K-Map 2.5.3 Using a 3-Variable K-Map 2.5.4 Using a 4-Variable K-Map 2.5.5 Don’t-Care Outputs Problems 3 Introduction to Logic Circuit Analysis and Design 3.1 Introduction 3.2 Integrated Circuit Devices 3.3 Analyzing and Designing Logic Circuits 3.3.1 Analyzing and Designing Relay Logic Circuits 3.3.2 Analyzing IC Logic Circuits 3.3.3 Designing IC Logic Circuits 3.4 Generating Detailed Schematics 3.5 Designing Circuits in NAND/NAND and NOR/NOR Form 3.6 Propagation Delay Time 3.7 Decoders 3.7.1 Designing Logic Circuits with Decoders and Single Gates 3.8 Multiplexers 3.8.1 Designing Logic Circuits with MUXs 3.9 Hazards 3.9.1 Function Hazards 3.9.2 Logic Hazards Problems 4 Combinational Logic Circuit Design with VHDL 4.1 Introduction 4.2 VHDL 4.3 The Library Part 4.4 The Entity Declaration 4.5 The Architecture Declaration 4.5.1 Comments about a Datafl ow Design Style 4.5.2 Comments about a Behavioral Design Style 4.5.3 Comments about a Structural Design Style 4.6 Datafl ow Design Style 4.7 Behavioral Design Style 4.8 Structural Design Style 4.9 Implementing with Wires and Buses 4.10 VHDL Examples 4.10.1 Design with Scalar Inputs and Outputs 4.10.2 Design with Vector Inputs and Outputs 4.10.3 Common VHDL Constructs Problems 5 Bistable Memory Device Design with VHDL 5.1 Introduction 5.2 Analyzing an S-R NOR Latch 5.2.1 Simple On/Off Light Switch 5.2.2 Circuit Delay Model for an S-R NOR Latch 5.2.3 Characteristic Table for an S-R NOR Latch 5.2.4 Characteristic Equation for an S-R NOR Latch 5.2.5 PS/NS Table for an S-R NOR Latch 5.2.5 Timing Diagram for an S-R NOR Latch 5.3 Analyzing an S-R NAND Latch 5.3.1 Circuit Delay Model for an S-R NAND Latch 5.3.2 Characteristic Table for an S-R NAND Latch 5.3.3 Characteristic Equation for an S-R NAND Latch 5.3.4 PS/NS Table for an S-R NAND Latch 5.3.5 Timing Diagram for an S-R NAND Latch 5.4 Designing a Simple Clock 5.5 Designing a D Latch 5.5.1 Gated S-R Latch Circuit Design 5.5.2 D Latch Circuit Design with S-R Latches 5.5.3 D Latch Circuit Design via the Characteristic Table for a D Latch 5.5.4 Timing Diagram for a D Latch 5.5.5 Creating a Clock via a D Latch 5.5.6 Creating an 8-bit D Latch 5.6 Designing D Flip-Flop Circuits 5.6.1 Designing Master–Slave D Flip-Flop Circuits 5.6.2 Designing D Flip-Flop Circuits with S-R NAND Latches 5.6.3 Timing Diagram for Positive Edge-Triggered D Flip-Flop Problems 6 Simple Finite State Machine Design with VHDL 6.1 Introduction 6.2 Synchronous Circuits 6.3 Creating D-type Flip-Flops in VHDL 6.4 Designing Simple Synchronous Circuits 6.5 Counter Design Using the Algorithmic Equation Method 6.6 Nonconventional Counter Design Using the Algorithmic Equation Method 6.7 Counter Design Using the Arithmetic Method 6.8 Frequency Division (Slowing Down a Fast Clock Frequency) 6.9 Counter Design Using the PS/NS Tabular Method 6.10 Nonconventional Counter Design Using the PS/NS Tabular Method Problems 7 Computer Circuits 7.1 Introduction 7.2 Three-State Outputs and the Disconnected State 7.3 Data Bus Sharing for a Microcomputer System 7.4 More about XOR and XNOR Symbols and Functions 7.4.1 Odd and Even Functions 7.4.2 Single-Bit Error Detection System 7.4.3 Comparators and Greater Than Circuits 7.5 Adder Design 7.5.1 Designing a Half Adder Module 7.5.2 Designing a Full Adder Module 7.6 Designing and Using Ripple-Carry Adders and Subtractors 7.7 Propagation Delay Time for Ripple-Carry Adders 7.8 Designing Carry Look-Ahead Adders 7.9 Propagation Delay Time for Carry Look-Ahead Adders Problems 8 Circuit Implementation Techniques 8.1 Introduction 8.2 Programmable Logic Devices 8.2.1 PROMs and LUTs 8.2.2 PLAs 8.2.3 PALs or GALs 8.2.4 Designing with PROMs or LUTs 8.2.5 Designing with PLAs 8.2.6 Designing with PALs or GALs 8.3 Positive Logic Convention and Direct Polarity Indication 8.3.1 Signal Names 8.3.2 Analyzing Equivalent Circuits for the PLC and the DPI Systems 8.4 More about MUXs and DMUXs 8.4.1 Designing MUX Trees 8.4.2 Designing DMUX Trees Problems 9 Complex Finite State Machine Design with VHDL 9.1 Introduction 9.2 Designing with the Two-Process PS/NS Method 9.3 Explanation of CPLDs and FPGAs and State Machine Encoding Styles 9.4 Summary of Finite State Machine Models 9.5 Designing Compact Encoded State Machines with Moore Outputs 9.6 Designing One-Hot Encoded State Machines with Moore Outputs 9.7 Designing Compact Encoded State Machines with Moore and Mealy Outputs 9.8 Designing One-Hot Encoded State Machines with Moore and Mealy Outputs 9.9 Using the Algorithmic Equation Method to Design Complex State Machines 9.10 Improving the Reliability of Complex State Machine Designs 9.11 Additional State Machine Design Methods 9.11.1 Two-Assignment PS/NS Method 9.11.2 Hybrid PS/NS Method Problems 10 Basic Computer Architectures 10.1 Introduction 10.2 Generic Data-Processing System or Computer 10.3 Harvard-Type Computer and RISC Architecture 10.4 Princeton (von Neumann)-Type Computer and CISC Architecture 10.5 Overview of VBC1 (Very Basic Computer 1) 10.6 Design Philosophy of VBC1 10.7 Programmer’s Register Model for VBC1 10.8 Instruction Set Architecture for VBC1 10.9 Format for Writing Assembly Language Programs Problems 11 Assembly Language Programming for VBC1 11.1 Introduction 11.2 Instruction Set for VBC1 11.3 The IN Instruction 11.4 The OUT Instruction 11.5 The MOV Instruction 11.6 The LOADI Instruction 11.7 The ADDI Instruction 11.8 The ADD Instruction 11.9 The SR0 Instruction 11.10 The JNZ Instruction 11.11 Programming Examples and Techniques for VBC1 11.11.1 Unconditional Jump 11.11.2 Labels 11.11.3 Loop Counter 11.11.4 Program Runs Amuck 11.11.5 Subtraction Instruction 11.11.6 Multiply Instruction 11.11.7 Divide Instruction 12 Designing Input/Output Circuits 12.1 Introduction 12.2 Designing Steering Circuits 12.3 Designing Bus Steering Circuits 12.4 Designing Loadable Register Circuits 12.5 Designing Input Circuits 12.5.1 Designing an Input Circuit Driven by Four Slide Switches 12.6 Designing Output Circuits 12.6.1 Designing an Output Circuit to Drive Four LEDs 12.6.2 Designing an Output Circuit to Drive a 7-Segment Display 12.6.3 A Closer Look at the Circuitry for Display 0 12.7 Combining Input and Output Circuits to Form a Simple I/O System 12.8 Alternate VHDL Design Styles Problems 13 Designing Instruction Memory, Loading Program Counter, and Debounced Circuit 13.1 Introduction 13.2 Designing an Instruction Memory 13.2.1 Coding Alterations for Instruction Memory 13.2.2 Initializing Instruction Memory for VBC1 at Startup 13.3 Designing a Loading Program Counter 13.4 Designing a Debounced One-Pulse Circuit 13.5 Design Verifi cation for a Debounced One-Pulse Circuit Problems 14 Designing Multiplexed Display Systems 14.1 Introduction 14.2 Multiplexed Display System for Four 7-Segment LED Displays 14.3 Designing a Multiplexed Display System Using VHDL 14.3.1 Designing Module 1: A 4-to-1 MUX Array 14.3.2 Designing Module 2: A HEX Display Decoder 14.3.3 Designing Module 3: A 2-bit Counter and a Frequency Divider 14.3.4 Designing Module 4: A 2-to-4 Decoder 14.4 Complete Design of a Multiplexed Display System Using a Flat Design Approach 14.5 Complete Design of a Multiplexed Display System Using a Hierarchal Design Approach 14.6 Designing a Word Display System Using a Flat Design Approach Problems 15 Designing Instruction Decoders 15.1 Introduction 15.2 Purpose of the Instruction Decoder 15.3 Instruction Decoder Truth Tables for the IN, OUT, and MOV Instructions 15.4 Designing an Instruction Decoder for the IN Instruction 15.5 Designing an Instruction Decoder for the OUT and MOV Instructions 15.6 Instruction Decoder Truth Table for the LOADI Instruction 15.7 Instruction Decoder Truth Table for the ADDI Instruction 15.8 Instruction Decoder Truth Table for the ADD Instruction 15.9 Instruction Decoder Truth Table for the SR Instruction 15.10 Designing an Instruction Decoder for the SR Instruction 15.11 Instruction Decoder Truth Table for the JNZ Instruction 15.12 Designing an Instruction Decoder for the JNZ Instruction 15.13 Designing an Instruction Decoder for VBC1 Problems 16 Designing Arithmetic Logic Units 16.1 Introduction 16.2 Utilization of the Arithmetic Logic Unit 16.3 Designing the LOADI Instruction Part of the ALU 16.4 Designing the ADDI Instruction Part of the ALU 16.5 Designing the ADD Instruction Part of the ALU 16.6 Designing the SR0 Instruction Part of the ALU 16.7 Designing an ALU for VBC1 16.8 Additional Circuit Designs with VHDL 16.8.1 Designing Additional ALU Circuits 16.8.2 Designing Shifter Circuits 16.8.3 Designing Barrel Shifter Circuits 16.8.4 Designing Shift Register Circuits Problems 17 Completing the Design for VBC1 17.1 Introduction 17.2 Designing a Running Program Counter 17.3 Combining a Loading and a Running Program Counter 17.4 Designing a Run Frequency Circuit and a Speed Circuit 17.5 Designing Circuits to Provide a Loader for Instruction Memory for VBC1 Problems 18 Assembly Language Programming for VBC1-E 18.1 Introduction 18.2 Instruction Summary 18.3 Input, Output, and Interrupt Instructions 18.4 Data Memory Instructions 18.5 Arithmetic and Logic Instructions 18.6 Shift and Rotate Instructions 18.7 Jump, Jump Relative, and Halt Instructions 18.8 More about Interrupts and Assembler Directives 18.9 Complete Instruction Set Summary for VBC1-E Problems 19 Designing Input/Output Circuits for VBC1-E 19.1 Introduction 19.2 Designing the Input Circuit for VBC1-E 19.3 Instruction Decoder Truth Table for the Modifi ed IN Instruction for VBC1-E 19.4 Designing the Output Circuit for VBC1-E 19.5 Instruction Decoder Truth Table for the Modifi ed OUT Instruction for VBC1-E 19.6 Designing an Instruction Decoder for the Modifi ed IN and OUT Instructions for VBC1-E 19.7 Designing an Instruction Decoder for the LOADI, ADDI, and JNZ Instructions for VBC1-E Problems 20 Designing the Data Memory Circuit for VBC1-E 20.1 Introduction 20.2 Designing the Data Memory for VBC1-E 20.3 Designing Circuits to Select the Registers and Data for VBC1-E 20.4 Instruction Decoder Truth Tables for the STORE and FETCH Instructions for VBC1-E 20.5 Designing an Instruction Decoder for the STORE and FETCH Instructions for VBC1-E 20.6 Designing an Instruction Decoder for the MOV Instruction for VBC1-E Problems 21 Designing the Arithmetic, Logic, Shift, Rotate, and Unconditional Jump Circuits for VBC1-E 21.1 Introduction 21.2 Designing the Arithmetic and Logic Instructions Part of the ALU for VBC1-E 21.3 Designing the Instruction Decoder for the Arithmetic and Logic Instructions for VBC1-E 21.4 Designing the Shift and Rotate Instructions Part of the ALU for VBC1-E 21.5 Designing the Instruction Decoder for the Shift and Rotate Instructions for VBC1-E 21.6 Designing the JMP and JMPR Circuits for VBC1-E 21.7 Designing the Instruction Decoder for the JMP and JMPR Instructions for VBC1-E Problems 22 Designing a Circuit to Prevent Program Execution During Manual Loading for VBC1-E 22.1 Introduction 22.2 Designing a Circuit to Modify Manual Loading for VBC1-E 22.3 Modifying the Instruction Decoder for Manual Loading for VBC1-E Problems 23 Designing Extended Instruction Memory for VBC1-E 23.1 Introduction 23.2 Modifying the Instruction Memory to Add Extended Instruction Memory for VBC1-E 23.3 Modifying the Running Program Counter Circuit for VBC1-E 23.4 Modifying the Proper Address Circuit for VBC1-E 23.5 Modifying the Loading Program Counter Circuit for VBC1-E 23.6 Modifying the JMPR Circuit for VBC1-E 24 Chapter Designing the Software Interrupt Circuits for VBC1-E 24.1 Introduction 24.2 Designing the Modifi ed Circuit for the Running Program Counter and the Select Circuit for VBC1-E 24.3 Designing the Circuit to Store PCPLUS1 for VBC1-E 24.4 Instruction Decoder Truth Tables for the INT and IRET Instructions for VBC1-E 24.5 Designing the Instruction Decoder for the INT and IRET Instructions for VBC1-E Problems 25 Completing the Design for VBC1-E 25.1 Introduction 25.2 Designing a Debounced One-Pulse Trigger Interrupt Circuit and Modifying the RPC Circuit for VBC1-E 25.3 Designing Circuits for Displaying the Signal RETA for VBC1-E 25.4 Designing Circuits to Provide a Loader for Instruction Memory for VBC1-E Problems Appendices A Laboratory Experiments Experiment 1A: Designing and Simulating Gates Experiment 1B: Completing the Design Cycle Experiment 2: Designing and Testing a Keypad Encoder System Experiment 3: Designing and Testing a Check Gates System Experiment 4: Designing and Testing a Custom Decimal Display Decoder System Experiment 5A: Designing and Testing a D Latch and a D Flip-Flop with a CLR Input Experiment 5B: Designing and Testing an 8-bit Register and a D Flip-Flop with a PRE Input Experiment 6A: Designing and Testing a Simple Counter System—A One-Hot Up Counter with BITS Experiment 6B: Designing and Testing a Simple Counter System—A Gray Code Counter with 2 Bits Experiment 6C: Designing and Testing a Simple Nonconventional Counter System—A Robot Eye Circuit Experiment 6D: Designing and Testing a Simple Nonconventional Counter—A Smiley Face Circuit Experiment 7A: Designing and Testing a Simple Error Detection System Using a Flat Design Approach Experiment 7B: Designing and Testing a 4-bit Simple Adder-Subtractor System Using a Hierarchal Design Approach Experiment 8: Designing and Testing a LUT Design System Using a Flat Design Approach Experiment 9A: Designing and Testing a One-Hot Up/ Down Counter System Using a Flat Design Approach Experiment 9B: Designing and Testing a 10-State Counter System Using a Hierarchal Design Approach Experiment 10: Working with EASY1 (Editor/Assembler/ Simulator) for VBC1 Experiment 11: Writing and Simulating Programs for VBC1 with EASY1 Experiment 12: Designing and Testing VBC1 (Data Path Unit) Experiment 13: Designing and Testing VBC1 (Instruction Memory Unit) Experiment 14: Designing and Testing VBC1 (Monitor System) Experiment 15: Designing and Testing VBC1 (Instruction Decoder ) Experiment 16: Designing and Testing VBC1 (Arithmetic Logic Unit) Experiment 17: Designing and Testing VBC1 (Final Hardware Design for VBC1) Experiment 17L: Designing a Loader for Instruction Memory for VBC1 Experiment 18 Writing Assembly Language Programs and Running Them on VBC1 Experiment 19: Designing and Testing VBC1-E (IN, OUT, and Unchanged Instructions) Experiment 20: Designing and Testing VBC1-E (MOV and Data Memory Instructions) Experiment 21: Designing and Testing VBC1-E (Almost All Instructions) Experiment 22: Designing and Testing VBC1-E (Modifi ed Manual Loading) Experiment 23: Designing and Testing VBC1-E (Add Extended Instruction Memory) Experiment 24: Designing and Testing VBC1-E (INT and IRET Instructions) Experiment 25: Designing and Testing VBC1-E (Final Hardware Design for VBC1-E) Experiment 25L: Designing a Loader for Instruction Memory for VBC1-E Obtaining Simulations via the VHDL Test Bench Program B.1 Introduction B.2 Example 1—Combinational Logic Design (project: AND_3) B.3 Example 2—Synchronous Sequential Logic Design (project: DFF) C FPGA Pin Connections—Handy Reference C.1 BASYS 2 Board C.2 NEXYS 2 Board C.3 Memory Loader I/O Pin Connections for the FPGAs on the BASYS 2 and NEXYS 2 Board C.4 FX2 MIB (Module Interface Board)—Add-on Board for NEXYS 2 D EASY1 Tutorial D.1 Introduction D.2 EASY1 Screen or GUI D.3 EASY1 Layout D.4 How to Use EASY1 D.5 Example 1—A Simple Input/Output Program D.6 Example 2—Input/Output Program Modifi ed to Run Continuously D.7 Example 3—A Simple State Machine Program D.8 Example 4—A Complex State Machine Program D.9 Example 5—Generating Time Delays D.10 Using EASY1 to Generate Machine Code for VBC1 E Three Methods for Loading Instructions into Memory E.1 Loading Memory Manually E.2 Initializing Memory at Startup E.3 Loading Memory via the Memory Loader Program Index