Deep Learning HDL Toolbox. User's Guide

Description

What is Deep Learning? Introduction to Deep Learning Training Process Training from Scratch Transfer Learning Feature Extraction Convolutional Neural Networks Deep Learning Processor Deep Learning Processor IP Core Architecture DDR Memory Memory Access Arbitrator Modules Convolution Kernel Top-Level Scheduler Module Fully Connected Kernel Custom Kernel Profiler Utilities Applications and Examples MATLAB Controlled Deep Learning Processor Deep Learning on FPGA Overview Deep Learning on FPGA Workflow Deep Learning on FPGA Solution Advantages of Deep Learning on FPGA Deep Learning on FPGA Workflows Workflow and APIS Prototype Deep Learning Networks on FPGA and SoC Devices Profile Inference Run Multiple Frame Support Input DDR Format Output DDR Format Manually Enable Multiple Frame Mode Initialize Deployed Deep Learning Processor Without Using a MATLAB Connection Prerequisites Generate File Generated File Structure Initiate Deployed Deep Learning Processor IP Core Fast MATLAB to FPGA Connection Using LIBIIO/Ethernet LIBIIO/Ethernet Connection Based Deep Learning Network Deployment Ethernet Interface LIBIIO/Ethernet Performance Networks and Layers Supported Networks, Layers, Boards, and Tools Supported Pretrained Networks Supported Layers Supported Boards Third-Party Synthesis Tools and Version Support Image Input Layer Normalization Hardware Implementation Custom Processor Configuration Workflow Custom Processor Configuration Workflow Estimate Performance of Deep Learning Network Estimate Performance of Custom Deep Learning Network for Custom Processor Configuration Evaluate Performance of Deep Learning Network on Custom Processor Configuration Estimate Resource Utilization for Custom Processor Configuration Estimate Resource Utilization Customize Bitstream Configuration to Meet Resource Use Requirements Effects of Custom Deep Learning Processor Parameters on Performance and Resource Utilization Generate Custom Bitstream to Meet Custom Deep Learning Network Requirements Create Deep Learning Processor Configuration for Custom Layers Deploy Custom Layer Networks Create a Deep learning Processor Configuration Create Custom Layer MATLAB Function Create Custom Layer Simulink Function Register Custom Layer and Model Generate Verification Model for Custom Layer Simulate and Validate Custom Layer Model Generate Custom Bitstream Deploy and Predict Custom Layer Network on Hardware Custom Layer Registration File Register, Validate, and Deploy Custom Natural Logarithm Layer Network to FPGA Custom Processor Code Generation Workflow Generate Custom Bitstream Generate Custom Processor IP Featured Examples Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC Get Started with Deep Learning FPGA Deployment on Xilinx ZCU102 SoC Get Started with Deep Learning FPGA Deployment on Xilinx ZC706 SoC Logo Recognition Network Deploy Transfer Learning Network for Lane Detection Image Category Classification by Using Deep Learning Defect Detection Profile Network to Determine Performance Bottlenecks Bicyclist and Pedestrian Classification by Using FPGA Visualize Activations of a Deep Learning Network by Using LogoNet Authoring a Reference Design for Live Camera Integration with Deep Learning Processor IP Core Run a Deep Learning Network on FPGA with Live Camera Input Running Convolution-Only Networks by Using FPGA Deployment Accelerate Prototyping Workflow for Large Networks by Using Ethernet Create Series Network for Quantization Custom Deep Learning Processor Generation to Meet Performance Requirements Quantize Network for FPGA Deployment Evaluate Performance of Deep Learning Network on Custom Processor Configuration Customize Bitstream Configuration to Meet Resource Use Requirements Vehicle Detection Using DAG Network Based YOLO v2 Deployed to FPGA Customize Bitstream Configuration to Meet Resource Use Requirements Image Classification Using Neural Network on FPGA Classify Images on FPGA Using Quantized Neural Network Classify ECG Signals Using DAG Network Deployed to FPGA Prototype and Verify Deep Learning Networks Without Target Hardware Classify Images on FPGA by Using Quantized GoogLeNet Network Estimate Resource Utilization for Custom Board and Reference Design Speech Command Recognition by Using FPGA Modulation Classification by Using FPGA Deploy Simple Adder Network by using MATLAB Deployment Script and Deployment Instructions File Human Pose Estimation by Using Segmentation DAG Network Deployed to FPGA Semantic Segmentation of Multispectral Images by Using Quantized U-Net on FPGA Optimize Deep Learning Processor Configuration for Network Performance Run Sequence-to-Sequence Classification on FPGAs by Using Deep Learning HDL Toolbox Generate Word-By-Word Text on FPGAs by Using Deep Learning HDL Toolbox Run Sequence Forecasting on FPGA by Using Deep Learning HDL Toolbox Detect Objects Using YOLO v3 Network Deployed to FPGA Run Sequence-to-Sequence Regression on FPGAs Deploy and Verify YOLO v2 Vehicle Detector on FPGA Deploy Semantic Segmentation Network Using Dilated Convolutions on FPGA Run Sequence Forecasting Using a GRU Layer on an FPGA Deploy YAMNet Networks to FPGAs With and Without Cross-Layer Equalization Increase Image Resolution Using VDSR Network Running on FPGA Deploy Image Recognition Network on FPGA With and Without Pruning Deep Learning Quantization Quantization Workflow Prerequisites Prerequisites for All Quantization Workflows Supported Networks and Layers Prerequisites for Calibration Prerequisites for Quantization Prerequisites for Validation Calibration Workflow Validation Workflow Code Generation and Deployment Deep Learning Processor IP Core User Guide Generate Custom Generic Deep Learning Processor IP Core Deep Learning Processor IP Core Use the Compiler Output for System Integration External Memory Address Map Compiler Optimizations Leg Level Compilations External Memory Data Format Key Terminology Convolution Module External Memory Data Format Fully Connected Module External Memory Data Format Deep Learning Processor IP Core Report Summary Target Interface Configuration Register Address Mapping IP Core User Guide IP Core File List Interface with the Deep Learning Processor IP Core Create Deep Learning Processor Configuration Select Data Processing Mode Design Processing Mode Interface Signals Design Batch Processing Mode Interface Design Streaming Mode Interface Access Data from DDR Deep Learning Processor IP Core Generation for Custom Board Deep Learning HDL Toolbox Support for LSTM Networks Support for Long Short-Term Memory Networks Prediction and Forecasting How Deep Learning HDL Toolbox Compiles the LSTM Layer LSTM Layer Architecture Compiler Interpretation How Deep Learning HDL Toolbox Compiles the GRU Layer