ENGLISH

A one-semester course in modeling of VLSI interconnections

By Goel , Ashok K

Book information

Publisher
Momentum Press
Year
2015
ISBN
1606505122, 978-1-60650-512-0, 978-1-60650-513-7, 1606505130
DOI
10.5643/9781606504871
Language
english
Format
PDF
Filesize
71 MB (74113297 bytes)
Series
Electronic circuits and semiconductor devices collection
Pages
362\362
Time added
2015-12-23 22:00:00
Integrated circuits -- Very large scale integratio

Description

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits

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