8th Generation Intel® Processor Family for S-Processor Platforms

Description

Document Number:336465-001 8th Generation Intel® Processor Family for S-Processor Platforms......Page 1 1 Introduction......Page 15 2.1 Register Terminology......Page 16 2.2 PCI Devices and Functions......Page 17 2.3 System Address Map......Page 19 2.4 Legacy Address Range......Page 22 2.4.6 Programmable Attribute Map (PAM) (C_0h – F_FFFFh)......Page 23 2.5 Main Memory Address Range (1 MB – TOLUD)......Page 25 2.5.4 Protected Memory Range (PMR) - (programmable)......Page 26 2.5.6 Pre-allocated Memory......Page 27 2.6 PCI Memory Address Range (TOLUD – 4 GB)......Page 28 2.6.4 High BIOS Area......Page 30 2.7.4 TSEG_BASE......Page 31 2.7.6 Indirect Accesses to MCHBAR Registers......Page 32 2.9 Graphics Memory Address Ranges......Page 33 2.10 System Management Mode (SMM)......Page 34 2.13 I/O Address Space......Page 35 2.13.1 PCI Express* I/O Address Mapping......Page 36 2.14.1 DMI Accesses to the Processor that Cross Device Boundaries......Page 37 2.14.2 Traffic Class (TC) / Virtual Channel (VC) Mapping Details......Page 38 2.16 Legacy VGA and I/O Range Decode Rules......Page 40 2.17 I/O Mapped Registers......Page 44 3 Host Bridge/DRAM Registers......Page 45 3.1 Vendor Identification (VID)—Offset 0h......Page 46 3.3 PCI Command (PCICMD)—Offset 4h......Page 47 3.4 PCI Status (PCISTS)—Offset 6h......Page 48 3.6 Class Code (CC)—Offset 9h......Page 50 3.7 Header Type (HDR)—Offset Eh......Page 51 3.9 Subsystem Identification (SID)—Offset 2Eh......Page 52 3.11 PCI Express* Egress Port Base Address (PXPEPBAR)—Offset 40h......Page 53 3.12 Host Memory Mapped Register Range Base (MCHBAR)—Offset 48h......Page 54 3.13 GMCH Graphics Control Register (GGC)—Offset 50h......Page 55 3.14 Device Enable (DEVEN)—Offset 54h......Page 56 3.15 Protected Audio Video Path Control (PAVPC)— Offset 58h......Page 58 3.16 DMA Protected Range (DPR)—Offset 5Ch......Page 60 3.17 PCI Express Register Range Base Address (PCIEXBAR)—Offset 60h......Page 61 3.18 Root Complex Register Range Base Address (DMIBAR)—Offset 68h......Page 62 3.19 Manageability Engine Base Address Register (MESEG)—Offset 70h......Page 63 3.20 Manageability Engine Limit Address Register (MESEG)—Offset 78h......Page 64 3.21 Programmable Attribute Map 0 (PAM0)—Offset 80h......Page 65 3.22 Programmable Attribute Map 1 (PAM1)—Offset 81h......Page 66 3.23 Programmable Attribute Map 2 (PAM2)—Offset 82h......Page 67 3.24 Programmable Attribute Map 3 (PAM3)—Offset 83h......Page 68 3.25 Programmable Attribute Map 4 (PAM4)—Offset 84h......Page 69 3.26 Programmable Attribute Map 5 (PAM5)—Offset 85h......Page 71 3.27 Programmable Attribute Map 6 (PAM6)—Offset 86h......Page 72 3.28 Legacy Access Control (LAC)—Offset 87h......Page 73 3.29 System Management RAM Control (SMRAMC)— Offset 88h......Page 76 3.30 Remap Base Address Register (REMAPBASE)— Offset 90h......Page 77 3.31 Remap Limit Address Register (REMAPLIMIT)— Offset 98h......Page 78 3.33 Top of Upper Usable DRAM (TOUUD)—Offset A8h......Page 79 3.34 Base Data of Stolen Memory (BDSM)—Offset B0h......Page 80 3.35 Base of GTT stolen Memory (BGSM)—Offset B4h......Page 81 3.37 Top of Low Usable DRAM (TOLUD)—Offset BCh......Page 82 3.39 Capabilities A (CAPID0)—Offset E4h......Page 84 3.40 Capabilities B (CAPID0)—Offset E8h......Page 85 3.41 Capabilities C (CAPID0)—Offset ECh......Page 87 4 Processor Graphics Registers......Page 88 4.2 Device Identification (DID2)—Offset 2h......Page 89 4.3 PCI Command (PCICMD)—Offset 4h......Page 90 4.4 PCI Status (PCISTS2)—Offset 6h......Page 91 4.5 Revision Identification (RID2)—Offset 8h......Page 92 4.7 Cache Line Size (CLS)—Offset Ch......Page 93 4.9 Header Type (HDR2)—Offset Eh......Page 94 4.10 Graphics Translation Table, Memory Mapped Range Address (GTTMMADR)—Offset 10h......Page 95 4.11 Graphics Memory Range Address (GMADR)— Offset 18h......Page 96 4.12 I/O Base Address (IOBAR)—Offset 20h......Page 97 4.13 Subsystem Vendor Identification (SVID2)—Offset 2Ch......Page 98 4.15 Video BIOS ROM Base Address (ROMADR)—Offset 30h......Page 99 4.17 Interrupt Line (INTRLINE)—Offset 3Ch......Page 100 4.18 Interrupt Pin (INTRPIN)—Offset 3Dh......Page 101 4.20 Maximum Latency (MAXLAT)—Offset 3Fh......Page 102 4.21 Capabilities A (CAPID0)—Offset 44h......Page 103 4.22 Capabilities B (CAPID0)—Offset 48h......Page 104 4.23 Device Enable (DEVEN0)—Offset 54h......Page 106 4.24 Base Data of Stolen Memory (BDSM)—Offset 5Ch......Page 107 4.25 Multi Size Aperture Control (MSAC)—Offset 62h......Page 108 4.27 Message Signaled Interrupts Capability ID (MSI)—Offset ACh......Page 110 4.28 Message Control (MC)—Offset AEh......Page 111 4.30 Message Data (MD)—Offset B4h......Page 112 4.31 Power Management Capabilities ID (PMCAPID)— Offset D0h......Page 113 4.32 Power Management Capabilities (PMCAP)—Offset D2h......Page 114 4.33 Power Management Control/Status (PMCS)— Offset D4h......Page 115 5.1 Device Enable (DEVEN)—Offset 54h......Page 116 5.2 Capabilities A (CAPID0)—Offset E4h......Page 117 5.3 Capabilities B (CAPID0)—Offset E8h......Page 119 6.1 DMI Virtual Channel Enhanced Capability (DMIVCECH)—Offset 0h......Page 121 6.2 DMI Port VC Capability Register 1 (DMIPVCCAP1)—Offset 4h......Page 122 6.4 DMI Port VC Control (DMIPVCCTL)—Offset Ch......Page 123 6.5 DMI VC0 Resource Capability (DMIVC0RCAP)— Offset 10h......Page 124 6.6 DMI VC0 Resource Control (DMIVC0RCTL)—Offset 14h......Page 125 6.7 DMI VC0 Resource Status (DMIVC0RSTS)—Offset 1Ah......Page 126 6.8 DMI VC1 Resource Capability (DMIVC1RCAP)— Offset 1Ch......Page 127 6.9 DMI VC1 Resource Control (DMIVC1RCTL)—Offset 20h......Page 128 6.10 DMI VC1 Resource Status (DMIVC1RSTS)—Offset 26h......Page 129 6.11 DMI VCm Resource Capability (DMIVCMRCAP)— Offset 34h......Page 130 6.12 DMI VCm Resource Control (DMIVCMRCTL)— Offset 38h......Page 131 6.13 DMI VCm Resource Status (DMIVCMRSTS)—Offset 3Eh......Page 132 6.14 DMI Root Complex Link Declaration (DMIRCLDECH)—Offset 40h......Page 133 6.15 DMI Element Self Description (DMIESD)—Offset 44h......Page 134 6.16 DMI Link Entry 1 Description (DMILE1D)—Offset 50h......Page 135 6.18 DMI Link Upper Entry 1 Address (DMILUE1A)— Offset 5Ch......Page 136 6.19 DMI Link Entry 2 Description (DMILE2D)—Offset 60h......Page 137 6.21 Link Capabilities (LCAP)—Offset 84h......Page 138 6.22 Link Control (LCTL)—Offset 88h......Page 140 6.23 DMI Link Status (LSTS)—Offset 8Ah......Page 141 6.24 Link Control 2 (LCTL2)—Offset 98h......Page 142 6.25 Link Status 2 (LSTS2)—Offset 9Ah......Page 144 7 MCHBAR Registers......Page 145 7.1 MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR— Offset 4000h......Page 147 7.2 MCHBAR_CH0_CR_SC_GS_CFG_0_0_0_MCHBAR— Offset 401Ch......Page 148 7.3 MCHBAR_CH0_CR_TC_ODT_0_0_0_MCHBAR— Offset 4070h......Page 150 7.4 Refresh parameters (TC)—Offset 4238h......Page 151 7.5 Refresh timing parameters (TC)—Offset 423Ch......Page 152 7.6 Power Management DIMM Idle Energy (PM)— Offset 4260h......Page 153 7.7 Power Management DIMM Power Down Energy (PM)—Offset 4264h......Page 154 7.8 Power Management DIMM Activate Energy (PM)— Offset 4268h......Page 155 7.9 Power Management DIMM RdCas Energy (PM)— Offset 426Ch......Page 156 7.10 Power Management DIMM WrCas Energy (PM)— Offset 4270h......Page 157 7.11 MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR— Offset 4400h......Page 158 7.12 MCHBAR_CH0_CR_SC_GS_CFG_0_0_0_MCHBAR— Offset 441Ch......Page 159 7.13 MCHBAR_CH0_CR_TC_ODT_0_0_0_MCHBAR— Offset 4470h......Page 161 7.14 Refresh parameters (TC)—Offset 4638h......Page 162 7.15 Refresh timing parameters (TC)—Offset 463Ch......Page 163 7.16 Power Management DIMM Idle Energy (PM)— Offset 4660h......Page 164 7.17 Power Management DIMM Power Down Energy (PM)—Offset 4664h......Page 165 7.18 Power Management DIMM Activate Energy (PM)— Offset 4668h......Page 166 7.19 Power Management DIMM RdCas Energy (PM)— Offset 466Ch......Page 167 7.20 Power Management DIMM WrCas Energy (PM)— Offset 4670h......Page 168 7.21 MCSCHEDS_CR_SC_GS_CFG_0_0_0_MCHBAR— Offset 4C1Ch......Page 169 7.22 PM—Offset 4C40h......Page 170 7.23 MCSCHEDS_CR_TC_ODT_0_0_0_MCHBAR—Offset 4C70h......Page 171 7.24 Refresh parameters (TC)—Offset 4E38h......Page 172 7.26 Power Management DIMM Idle Energy (PM)— Offset 4E60h......Page 173 7.27 Power Management DIMM Power Down Energy (PM)—Offset 4E64h......Page 174 7.28 Power Management DIMM Activate Energy (PM)— Offset 4E68h......Page 175 7.29 Power Management DIMM RdCas Energy (PM)— Offset 4E6Ch......Page 176 7.30 Power Management DIMM WrCas Energy (PM)— Offset 4E70h......Page 177 7.31 Address decoder inter channel configuration register (MAD)—Offset 5000h......Page 178 7.32 Address decoder intra channel configuration register (MAD)—Offset 5004h......Page 179 7.33 Address decoder intra channel configuration register (MAD)—Offset 5008h......Page 180 7.34 Address decode DIMM parameters. (MAD)—Offset 500Ch......Page 181 7.35 Address decode DIMM parameters (MAD)—Offset 5010h......Page 183 7.37 Request count from GT (DRAM)—Offset 5040h......Page 184 7.38 Request count from IA (DRAM)—Offset 5044h......Page 185 7.40 RD data count (DRAM)—Offset 5050h......Page 186 7.41 WR data count (DRAM)—Offset 5054h......Page 187 7.43 NCDECS_CR_GFXVTBAR_0_0_0_MCHBAR_NCU— Offset 5400h......Page 188 7.44 NCDECS_CR_VTDPVC0BAR_0_0_0_MCHBAR_NCU—Of fset 5410h......Page 189 7.45 PACKAGE—Offset 5820h......Page 190 7.47 PKG—Offset 5830h......Page 192 7.49 PKG—Offset 5840h......Page 193 7.51 PKG—Offset 5858h......Page 194 7.52 DDR—Offset 5880h......Page 195 7.53 DRAM—Offset 5884h......Page 196 7.54 DRAM—Offset 5888h......Page 197 7.55 DDR—Offset 588Ch......Page 198 7.57 DDR—Offset 5894h......Page 199 7.58 DDR—Offset 5898h......Page 200 7.60 DDR—Offset 58A0h......Page 201 7.61 PACKAGE—Offset 58A8h......Page 203 7.62 DDR—Offset 58B0h......Page 204 7.64 DDR—Offset 58C0h......Page 205 7.65 DDR—Offset 58C8h......Page 206 7.67 DDR—Offset 58D4h......Page 207 7.68 DDR—Offset 58D8h......Page 208 7.70 PACKAGE—Offset 58F0h......Page 209 7.71 IA—Offset 58FCh......Page 210 7.72 GT—Offset 5900h......Page 212 7.73 SA—Offset 5918h......Page 214 7.74 GT—Offset 5948h......Page 215 7.76 Package—Offset 5978h......Page 216 7.78 PP1—Offset 5980h......Page 217 7.79 RP—Offset 5994h......Page 218 7.80 RP—Offset 5998h......Page 219 7.82 BIOS—Offset 5DA8h......Page 220 7.83 PCU_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PCU— Offset 5E00h......Page 221 7.84 CONFIG—Offset 5F3Ch......Page 222 7.85 CONFIG—Offset 5F40h......Page 223 7.86 CONFIG—Offset 5F48h......Page 224 7.87 CONFIG—Offset 5F50h......Page 225 7.88 TURBO—Offset 5F54h......Page 226 7.89 Package Thermal DPPM Status (PKG)—Offset 6200h......Page 227 7.90 Memory Thermal DPPM Status (DDR)—Offset 6204h......Page 228 8 GFXVTBAR Registers......Page 230 8.2 Capability Register (CAP)—Offset 8h......Page 231 8.3 Extended Capability Register (ECAP)—Offset 10h......Page 234 8.4 Global Command Register (GCMD)—Offset 18h......Page 236 8.5 Global Status Register (GSTS)—Offset 1Ch......Page 239 8.6 Root-Entry Table Address Register (RTADDR)— Offset 20h......Page 240 8.7 Context Command Register (CCMD)—Offset 28h......Page 241 8.8 Fault Status Register (FSTS)—Offset 34h......Page 243 8.9 Fault Event Control Register (FECTL)—Offset 38h......Page 244 8.11 Fault Event Address Register (FEADDR)—Offset 40h......Page 246 8.13 Advanced Fault Log Register (AFLOG)—Offset 58h......Page 247 8.14 Protected Memory Enable Register (PMEN)— Offset 64h......Page 248 8.15 Protected Low-Memory Base Register (PLMBASE)—Offset 68h......Page 249 8.16 Protected Low-Memory Limit Register (PLMLIMIT)—Offset 6Ch......Page 250 8.17 Protected High-Memory Base Register (PHMBASE)—Offset 70h......Page 251 8.18 Protected High-Memory Limit Register (PHMLIMIT)—Offset 78h......Page 252 8.19 Invalidation Queue Head Register (IQH)—Offset 80h......Page 253 8.20 Invalidation Queue Tail Register (IQT)—Offset 88h......Page 254 8.21 Invalidation Queue Address Register (IQA)— Offset 90h......Page 255 8.22 Invalidation Completion Status Register (ICS)— Offset 9Ch......Page 256 8.23 Invalidation Event Control Register (IECTL)— Offset A0h......Page 257 8.25 Invalidation Event Address Register (IEADDR)— Offset A8h......Page 258 8.26 Invalidation Event Upper Address Register (IEUADDR)—Offset ACh......Page 259 8.27 Interrupt Remapping Table Address Register (IRTA)—Offset B8h......Page 260 8.29 Fault Recording High Register (FRCDH)—Offset 408h......Page 261 8.30 Invalidate Address Register (IVA)—Offset 500h......Page 263 8.31 IOTLB Invalidate Register (IOTLB)—Offset 508h......Page 264 8.32 DMA Remap Engine Policy Control (ARCHDIS)— Offset FF0h......Page 266 8.33 DMA Remap Engine Policy Control (UARCHDIS)— Offset FF4h......Page 268 9.1 EP VC 0 Resource Control (EPVC0RCTL)—Offset 14h......Page 270 10 VC0PREMAP Registers......Page 272 10.2 Capability Register (CAP)—Offset 8h......Page 273 10.3 Extended Capability Register (ECAP)—Offset 10h......Page 276 10.4 Global Command Register (GCMD)—Offset 18h......Page 278 10.5 Global Status Register (GSTS)—Offset 1Ch......Page 281 10.6 Root-Entry Table Address Register (RTADDR)— Offset 20h......Page 282 10.7 Context Command Register (CCMD)—Offset 28h......Page 283 10.8 Fault Status Register (FSTS)—Offset 34h......Page 285 10.9 Fault Event Control Register (FECTL)—Offset 38h......Page 286 10.11 Fault Event Address Register (FEADDR)—Offset 40h......Page 288 10.13 Advanced Fault Log Register (AFLOG)—Offset 58h......Page 289 10.14 Protected Memory Enable Register (PMEN)— Offset 64h......Page 290 10.15 Protected Low-Memory Base Register (PLMBASE)—Offset 68h......Page 291 10.16 Protected Low-Memory Limit Register (PLMLIMIT)—Offset 6Ch......Page 292 10.17 Protected High-Memory Base Register (PHMBASE)—Offset 70h......Page 293 10.18 Protected High-Memory Limit Register (PHMLIMIT)—Offset 78h......Page 294 10.19 Invalidation Queue Head Register (IQH)—Offset 80h......Page 295 10.20 Invalidation Queue Tail Register (IQT)—Offset 88h......Page 296 10.22 Invalidation Completion Status Register (ICS)— Offset 9Ch......Page 297 10.23 Invalidation Event Control Register (IECTL)— Offset A0h......Page 298 10.24 Invalidation Event Data Register (IEDATA)— Offset A4h......Page 299 10.25 Invalidation Event Address Register (IEADDR)— Offset A8h......Page 300 10.27 Interrupt Remapping Table Address Register (IRTA)—Offset B8h......Page 301 10.28 Fault Recording Low Register (FRCDL)—Offset 400h......Page 302 10.29 Fault Recording High Register (FRCDH)—Offset 408h......Page 303 10.30 Invalidate Address Register (IVA)—Offset 500h......Page 304 10.31 IOTLB Invalidate Register (IOTLB)—Offset 508h......Page 305 11 PCI Express* Controller (x16) Registers......Page 308 11.1 Vendor Identification (VID)—Offset 0h......Page 309 11.3 PCI Command (PCICMD)—Offset 4h......Page 310 11.4 PCI Status (PCISTS)—Offset 6h......Page 312 11.5 Revision Identification (RID)—Offset 8h......Page 314 11.7 Cache Line Size (CL)—Offset Ch......Page 315 11.9 Primary Bus Number (PBUSN)—Offset 18h......Page 316 11.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah......Page 317 11.13 I/O Limit Address (IOLIMIT)—Offset 1Dh......Page 318 11.14 Secondary Status (SSTS)—Offset 1Eh......Page 319 11.15 Memory Base Address (MBASE)—Offset 20h......Page 320 11.16 Memory Limit Address (MLIMIT)—Offset 22h......Page 321 11.18 Prefetchable Memory Limit Address (PMLIMIT)— Offset 26h......Page 322 11.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h......Page 323 11.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch......Page 324 11.22 Interrupt Line (INTRLINE)—Offset 3Ch......Page 325 11.23 Interrupt Pin (INTRPIN)—Offset 3Dh......Page 326 11.24 Bridge Control (BCTRL)—Offset 3Eh......Page 327 11.25 Power Management Capabilities (PM)—Offset 80h......Page 328 11.26 Power Management Control/Status (PM)—Offset 84h......Page 329 11.27 Subsystem ID and Vendor ID Capabilities (SS)— Offset 88h......Page 330 11.28 Subsystem ID and Subsystem Vendor ID (SS)— Offset 8Ch......Page 331 11.30 Message Control (MC)—Offset 92h......Page 332 11.31 Message Address (MA)—Offset 94h......Page 333 11.33 PCI Express-G Capability List (PEG)—Offset A0h......Page 334 11.34 PCI Express-G Capabilities (PEG)—Offset A2h......Page 335 11.36 Device Control (DCTL)—Offset A8h......Page 336 11.37 Device Status (DSTS)—Offset AAh......Page 338 11.38 Link Capability (LCAP)—Offset ACh......Page 339 11.39 Link Control (LCTL)—Offset B0h......Page 340 11.40 Link Status (LSTS)—Offset B2h......Page 342 11.41 Slot Capabilities (SLOTCAP)—Offset B4h......Page 343 11.42 Slot Control (SLOTCTL)—Offset B8h......Page 344 11.43 Slot Status (SLOTSTS)—Offset BAh......Page 346 11.44 Root Control (RCTL)—Offset BCh......Page 348 11.45 Root Status (RSTS)—Offset C0h......Page 349 11.46 Device Capabilities 2 (DCAP2)—Offset C4h......Page 350 11.47 Device Control 2 (DCTL2)—Offset C8h......Page 352 11.48 Link Control 2 (LCTL2)—Offset D0h......Page 353 11.49 Link Status 2 (LSTS2)—Offset D2h......Page 355 11.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h......Page 356 11.52 Port VC Control (PVCCTL)—Offset 10Ch......Page 357 11.53 VC0 Resource Capability (VC0RCAP)—Offset 110h......Page 358 11.54 VC0 Resource Control (VC0RCTL)—Offset 114h......Page 359 11.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah......Page 360 11.57 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h......Page 361 11.59 PEG Root Error Status—Offset 1F0h......Page 362 11.60 PEG Error Source Identification—Offset 1F4h......Page 363 12 PCI Express* Controller (x8) Registers......Page 364 12.1 Vendor Identification (VID)—Offset 0h......Page 365 12.3 PCI Command (PCICMD)—Offset 4h......Page 366 12.4 PCI Status (PCISTS)—Offset 6h......Page 368 12.5 Revision Identification (RID)—Offset 8h......Page 370 12.7 Cache Line Size (CL)—Offset Ch......Page 371 12.9 Primary Bus Number (PBUSN)—Offset 18h......Page 372 12.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah......Page 373 12.13 I/O Limit Address (IOLIMIT)—Offset 1Dh......Page 374 12.14 Secondary Status (SSTS)—Offset 1Eh......Page 375 12.15 Memory Base Address (MBASE)—Offset 20h......Page 376 12.16 Memory Limit Address (MLIMIT)—Offset 22h......Page 377 12.18 Prefetchable Memory Limit Address (PMLIMIT)— Offset 26h......Page 378 12.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h......Page 379 12.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch......Page 380 12.22 Interrupt Line (INTRLINE)—Offset 3Ch......Page 381 12.23 Interrupt Pin (INTRPIN)—Offset 3Dh......Page 382 12.24 Bridge Control (BCTRL)—Offset 3Eh......Page 383 12.25 Power Management Capabilities (PM)—Offset 80h......Page 384 12.26 Power Management Control/Status (PM)—Offset 84h......Page 385 12.27 Subsystem ID and Vendor ID Capabilities (SS)— Offset 88h......Page 386 12.28 Subsystem ID and Subsystem Vendor ID (SS)— Offset 8Ch......Page 387 12.30 Message Control (MC)—Offset 92h......Page 388 12.31 Message Address (MA)—Offset 94h......Page 389 12.33 PCI Express-G Capability List (PEG)—Offset A0h......Page 390 12.34 PCI Express-G Capabilities (PEG)—Offset A2h......Page 391 12.35 Device Capabilities (DCAP)—Offset A4h......Page 392 12.36 Device Control (DCTL)—Offset A8h......Page 393 12.37 Device Status (DSTS)—Offset AAh......Page 394 12.38 Link Capability (LCAP)—Offset ACh......Page 395 12.39 Link Control (LCTL)—Offset B0h......Page 396 12.40 Link Status (LSTS)—Offset B2h......Page 398 12.41 Slot Capabilities (SLOTCAP)—Offset B4h......Page 399 12.42 Slot Control (SLOTCTL)—Offset B8h......Page 401 12.43 Slot Status (SLOTSTS)—Offset BAh......Page 402 12.44 Root Control (RCTL)—Offset BCh......Page 404 12.45 Root Status (RSTS)—Offset C0h......Page 405 12.46 Device Capabilities 2 (DCAP2)—Offset C4h......Page 406 12.47 Device Control 2 (DCTL2)—Offset C8h......Page 408 12.48 Link Control 2 (LCTL2)—Offset D0h......Page 409 12.49 Link Status 2 (LSTS2)—Offset D2h......Page 411 12.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h......Page 412 12.52 Port VC Control (PVCCTL)—Offset 10Ch......Page 413 12.53 VC0 Resource Capability (VC0RCAP)—Offset 110h......Page 414 12.54 VC0 Resource Control (VC0RCTL)—Offset 114h......Page 415 12.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah......Page 416 12.57 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h......Page 417 12.59 PEG Root Error Status—Offset 1F0h......Page 418 12.60 PEG Error Source Identification—Offset 1F4h......Page 419 13 PCI Express* Controller (x4) Registers......Page 420 13.1 Vendor Identification (VID)—Offset 0h......Page 421 13.3 PCI Command (PCICMD)—Offset 4h......Page 422 13.4 PCI Status (PCISTS)—Offset 6h......Page 424 13.5 Revision Identification (RID)—Offset 8h......Page 425 13.7 Cache Line Size (CL)—Offset Ch......Page 426 13.9 Primary Bus Number (PBUSN)—Offset 18h......Page 427 13.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah......Page 428 13.12 I/O Base Address (IOBASE)—Offset 1Ch......Page 429 13.14 Secondary Status (SSTS)—Offset 1Eh......Page 430 13.15 Memory Base Address (MBASE)—Offset 20h......Page 431 13.16 Memory Limit Address (MLIMIT)—Offset 22h......Page 432 13.17 Prefetchable Memory Base Address (PMBASE)— Offset 24h......Page 433 13.18 Prefetchable Memory Limit Address (PMLIMIT)— Offset 26h......Page 434 13.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h......Page 435 13.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch......Page 436 13.22 Interrupt Line (INTRLINE)—Offset 3Ch......Page 437 13.24 Bridge Control (BCTRL)—Offset 3Eh......Page 438 13.25 Power Management Capabilities (PM)—Offset 80h......Page 440 13.26 Power Management Control/Status (PM)—Offset 84h......Page 441 13.27 Subsystem ID and Vendor ID Capabilities (SS)— Offset 88h......Page 442 13.28 Subsystem ID and Subsystem Vendor ID (SS)— Offset 8Ch......Page 443 13.30 Message Control (MC)—Offset 92h......Page 444 13.31 Message Address (MA)—Offset 94h......Page 445 13.33 PCI Express-G Capability List (PEG)—Offset A0h......Page 446 13.35 Device Capabilities (DCAP)—Offset A4h......Page 447 13.36 Device Control (DCTL)—Offset A8h......Page 448 13.37 Device Status (DSTS)—Offset AAh......Page 449 13.38 Link Capability (LCAP)—Offset ACh......Page 450 13.39 Link Control (LCTL)—Offset B0h......Page 452 13.40 Link Status (LSTS)—Offset B2h......Page 453 13.41 Slot Capabilities (SLOTCAP)—Offset B4h......Page 455 13.42 Slot Control (SLOTCTL)—Offset B8h......Page 456 13.43 Slot Status (SLOTSTS)—Offset BAh......Page 458 13.44 Root Control (RCTL)—Offset BCh......Page 459 13.45 Root Status (RSTS)—Offset C0h......Page 460 13.46 Device Capabilities 2 (DCAP2)—Offset C4h......Page 461 13.47 Device Control 2 (DCTL2)—Offset C8h......Page 463 13.48 Link Control 2 (LCTL2)—Offset D0h......Page 464 13.49 Link Status 2 (LSTS2)—Offset D2h......Page 466 13.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h......Page 467 13.52 Port VC Control (PVCCTL)—Offset 10Ch......Page 468 13.53 VC0 Resource Capability (VC0RCAP)—Offset 110h......Page 469 13.54 VC0 Resource Control (VC0RCTL)—Offset 114h......Page 470 13.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah......Page 471 13.57 PEG Header Log—Offset 1DCh, 1E0h, 1E4h, 1E8h......Page 472 13.59 PEG Root Error Status—Offset 1F0h......Page 473 13.60 PEG Error Source Identification—Offset 1F4h......Page 474 14.1 Top of Low Usable DRAM (MTOLUD)—Offset 108000h......Page 475 14.2 Top of Upper Usable DRAM (MTOUUD)—Offset 108080h......Page 476 14.3 Base Data of Stolen Memory (MBDSM)—Offset 1080C0h......Page 477 14.4 Base of GTT stolen Memory (MBGSM)—Offset 108100h......Page 478 14.5 Protected Memory Enable Register (MPMEN)— Offset 108180h......Page 479 14.6 Protected Low-Memory Base Register (MPLMBASE)—Offset 1081C0h......Page 480 14.7 Protected Low-Memory Limit Register (MPLMLIMIT)—Offset 108200h......Page 481 14.8 Protected High-Memory Base Register (MPHMBASE)—Offset 108240h......Page 482 14.9 Protected High-Memory Limit Register (MPHMLIMIT)—Offset 108280h......Page 483 14.10 Protected Audio Video Path Control (MPAVPC)— Offset 1082C0h......Page 484 14.11 Global Command Register (MGCMD)—Offset 108300h......Page 486