Power Integrity Analysis and Management for Integrated Circuits (Prentice Hall Modern Semiconductor Design)

Description

New Techniques and Tools for Ensuring On-Chip Power Integrity―Down to Nanoscale   As chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem solving.   Raj Nair and Dr. Donald Bennett first provide a complete foundational understanding of power integrity, including ULSI issues, practical aspects of power delivery, and the benefits of a total power integrity approach to optimizing chip physical designs. They introduce advanced power distribution network modeling, design, and analysis techniques that highlight abstraction and physics-based analysis, while also incorporating traditional circuit- and field-solver based approaches. They also present advanced techniques for floorplanning and power integrity management, and help designers anticipate emerging challenges associated with increased integration. Anasim RLCSim.exe, a new tool for power integrity aware floorplanning, is downloadable for free at anasim.com/category/software.   The authors Systematically explore power integrity implications, analysis, and management for integrated circuits Present practical examples and industry best practices for a broad spectrum of chip design applications Discuss distributed and high-bandwidth voltage regulation, differential power path design, and the significance of on-chip inductance to power integrity Review both traditional and advanced modeling techniques for integrated circuit power integrity analysis, and introduce continuum modeling Explore chip, package, and board interactions for power integrity and EMI, and bring together industry best practices and examples Introduce advanced concepts for power integrity management, including non-linear capacitance devices, impedance modulation, and active noise regulation   Power Integrity Analysis and Management for Integrated Circuits’ coverage of both fundamentals and advanced techniques will make this book indispensable to all engineers responsible for signal integrity, power integrity, hardware, or system design―especially those working at the nanoscale level. Cover Contents Preface Acknowledgments About the Authors Contributors Chapter 1 Power, Delivering Power, and Power Integrity 1.1 Electromotive Force (emf) 1.1.1 Force-Voltage Analogy 1.2 Electrical Power 1.2.1 Physical Analogy for Power 1.2.2 Sources of Electrical Power 1.2.3 Powering Electrical and Electronic Circuits and Systems 1.3 Power Delivery 1.3.1 Central DC Power Delivery Module 1.3.2 Integrated Power Delivery 1.3.3 Power Distribution Networks 1.3.4 Power Delivery Regulation 1.4 Power Integrity (PI) 1.4.1 Contributors to PI Degradation 1.5 Exercises References Chapter 2 Ultra-Large-Scale Integration and Power Challenges 2.1 Exponential Integration and Semiconductor Scaling 2.1.1 Microprocessor Architecture Power Trend 2.1.2 Scaling of Transistor Dimensions and Its Impact 2.2 Power and Energy Consumption 2.2.1 Power and Energy Expenditure in Charging a Capacitor 2.2.2 Other Sources of Power Consumption 2.3 Power, Heat, and Power Integrity Challenges 2.3.1 Power Integrity and the Impact of Scaling 2.4 Exercises References Chapter 3 IC Power Integrity and Optimal Power Delivery 3.1 Power Transfer and Efficiency 3.1.1 Maximum Power Transfer Theorem 3.1.2 IC Power Supplies 3.1.3 Supply Noise and the Differential Nature of Closed-Loop Power Transfer 3.1.4 Noise and Total Power Integrity 3.2 Optimal IC Power Delivery: On-Chip Inductance and Grid Design 3.2.1 Equivalent Circuit Model for On-Chip Power Grid Analysis 3.2.2 Noise Dependency on Slope of Load Current and Capacitance Position 3.2.3 Power Grid Analysis Focusing Distribution of Power Consumption 3.2.4 Power Grid Design for Robustness with On-Chip Inductance 3.3 Power Grid Cost Factor Trade-off Analysis and Design 3.3.1 Cost Factors for Power Distribution Grid Design 3.3.2 Trade-off Analysis for Power Distribution Grid Design 3.4 Exercises References Chapter 4 Early Power Integrity Analysis and Abstraction 4.1 Process, Voltage, and Temperature: Design Verification Space 4.1.1 Supply Variability Allocation 4.2 Back-End and Front-End PI Analysis 4.2.1 Gaps in IC PI Analysis 4.2.2 Front-End PI Analysis 4.2.3 Abstraction of Chip Components 4.3 Simulation Environment for Models of High Abstraction Levels 4.3.1 Continuum Models 4.4 Abstraction and PI Analysis Examples 4.4.1 Optimal On-Chip Power Network Design 4.4.2 System-Level Front-End Simulation 4.5 Summary and Enhancements 4.6 Exercises References Chapter 5 Power Integrity Analysis and EMI/EMC 5.1 Introduction 5.2 Analysis of Noise Generation and Propagation through a Power Distribution Network 5.2.1 Sources of Power and Ground Noise 5.2.2 Calculating the Target Impedance of a PDN 5.2.3 Estimation of Power-Ground Noise from PDN Impedance 5.3 Modeling Decoupling Capacitors for Noise Mitigation in PDNs 5.3.1 On-Board Decoupling Capacitors 5.3.2 On-Package Decoupling Capacitance 5.3.3 On-Chip Decoupling Capacitors 5.4 Current Design Methodology for Power Delivery Networks 5.4.1 Step 1: Reduce the PDN Inductance as Much as Possible 5.4.2 Step 2: The Use of Board Decoupling Capacitors 5.4.3 Step 3: The Use of Package Decoupling Capacitors 5.4.4 Step 4: Use of On-Chip Decoupling Capacitors 5.5 Modeling Methodologies 5.5.1 Approximations Based on Lower Frequency 5.5.2 Higher-Frequency Methods 5.5.3 Classification of Numerical Methodologies 5.5.4 A Case Study to Compare Numerical Methods 5.6 Numerical Methods 5.6.1 Integral Equation Methods 5.6.2 Differential Equation Methods 5.7 Power and Signal Delivery Analysis Tools and Limitations 5.7.1 Limitations Based on Tool Categories 5.7.2 Illustration of Tool Limitations 5.8 Power Integrity-Aware Electromagnetic Interference Analysis 5.8.1 Components of a PDN and Associated Power Integrity Issues 5.8.2 System-Level Power Rail Noise Due to SSO/SSN High-Current Transients 5.8.3 Package and PCB Plane Resonance 5.8.4 System-Level Decoupling Optimization 5.8.5 Return Reference Plane Discontinuity 5.9 Strengths and Limitations of Existing Early EMI methodologies 5.10 Early Power Integrity-Aware EMI Modeling and Analysis Flow 5.10.1 Components of an Early Power Integrity-Aware EMI Flow 5.11 SI, PI, and EMI Summary 5.12 Exercises References Chapter 6 Power Distribution Modeling and Integrity Analysis 6.1 Introduction 6.2 Modeling of a Power Distribution Grid 6.3 Numerical Analysis of Power Distribution Model 6.4 Differential and Common-Mode Noise 6.5 Verification and Error Analysis 6.6 Modeling of On-Chip Bus Switching Current 6.7 Verification of the Bus Model 6.8 Bus Skewing to Reduce Power Distribution Noise 6.9 Case Study: Reduction of Power Distribution Noise 6.10 Exercises 6.11 Appendix: Coefficients for Equation (6-37) References Chapter 7 Effective Current Density and Continuum Models 7.1 Circuit and Model Simplification 7.2 Definition of Effective Current Density 7.3 Effective Current Density and Virtual Currents 7.4 Symmetry in Networks Containing Conductors, Insulators, and Other Components 7.5 A Continuum Model Using ECD 7.6 Practical Application of a Continuum-Based Simulator to IC Floorplanning 7.7 Continuum Models Compared to SPICE Models 7.8 Model Enhancement for Nanoscale CMOS Integrated Circuits 7.9 Exercises References Chapter 8 Power Integrity-Aware Chip Floorplanning and Design 8.1 Design for Power Integrity: Nanometer Era Considerations 8.1.1 System Requirements 8.1.2 Die Cost 8.1.3 Performance 8.1.4 Power Minimization 8.1.5 Other Considerations 8.2 Design for Power Integrity: Techniques 8.2.1 Power Consumption Management 8.2.2 Power Grid Design 8.2.3 Chip Floorplanning and Decoupling Capacitance 8.3 Power Management and Power Integrity 8.3.1 Power Management Techniques 8.3.2 Power Integrity Implications References Chapter 9 Power Integrity Management in Integrated Circuits and Systems 9.1 Chip-Level PI Management 9.1.1 Primary Techniques 9.1.2 On-Chip Noise Measurement and Modeling 9.1.3 Voltage-Dependent Decoupling Capacitance 9.1.4 Advanced Aspects and Techniques 9.2 System- and Package-Level PI Management 9.2.1 System-Level PI Management 9.2.2 Package-Mounted Capacitors 9.2.3 Active Packaging and Active Noise Regulation 9.2.4 Package PI Management Summary 9.3 Exercises References Additional Reading Chapter 10 Integration Technologies, Trends, and Challenges 10.1 Chip-Level Integration 10.1.1 Device Architecture for Low-Power Systems 10.1.2 Beneficial Applications of Multiple Independent-Gate FinFETs 10.1.3 Device Architecture Summary 10.2 Package-Level Integration 10.2.1 Advanced Packaging Technologies 10.3 Integration Trend for Power Integrity Management Components References Additional Reading Appendix A: ECD Continuum Model Derivation Appendix B: Derivation of the Helmholtz Equation for Planar Circuits Index A B C D E F H H I J K L M N O P Q R S T U V W Z