ENGLISH

5-Level Paging and 5-Level EPT White Paper

By coll.

Book information

Publisher
Intel Corporation
Year
2016
Language
english
Format
PDF
Filesize
195 kB (199550 bytes)
Series
Document Number: 335252-001
Edition
Revision 1.0
Pages
26\26
Scanned
yes
Time added
2017-05-09 22:08:14

Description

This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware. Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.

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